mcore.md

linux下的gcc编译器

	(match_operand:SI 0 "mcore_arith_reg_operand" "r"))]
  ""
  "jmp	%0"
  [(set_attr "type" "jmp")])

(define_expand "call"
  [(parallel[(call (match_operand:SI 0 "" "")
		   (match_operand 1 "" ""))
	     (clobber (reg:SI 15))])]
  ""
  "
{
  if (GET_CODE (operands[0]) == MEM
      && ! register_operand (XEXP (operands[0], 0), SImode)
      && ! mcore_symbolic_address_p (XEXP (operands[0], 0)))
    operands[0] = gen_rtx (MEM, GET_MODE (operands[0]),
			   force_reg (Pmode, XEXP (operands[0], 0)));
}")

(define_insn "call_internal"
  [(call (mem:SI (match_operand:SI 0 "mcore_call_address_operand" "riR"))
	 (match_operand 1 "" ""))
   (clobber (reg:SI 15))]
  ""
  "* return mcore_output_call (operands, 0);")

(define_expand "call_value"
  [(parallel[(set (match_operand 0 "register_operand" "")
		  (call (match_operand:SI 1 "" "")
			(match_operand 2 "" "")))
	     (clobber (reg:SI 15))])]
  ""
  "
{
  if (GET_CODE (operands[0]) == MEM
      && ! register_operand (XEXP (operands[0], 0), SImode)
      && ! mcore_symbolic_address_p (XEXP (operands[0], 0)))
    operands[1] = gen_rtx (MEM, GET_MODE (operands[1]),
			   force_reg (Pmode, XEXP (operands[1], 0)));
}")

(define_insn "call_value_internal"
  [(set (match_operand 0 "register_operand" "=r")
	(call (mem:SI (match_operand:SI 1 "mcore_call_address_operand" "riR"))
	      (match_operand 2 "" "")))
   (clobber (reg:SI 15))]
  ""
  "* return mcore_output_call (operands, 1);")

(define_insn "call_value_struct"
  [(parallel [(set (match_parallel 0 ""
	             [(expr_list (match_operand 3 "register_operand" "") (match_operand 4 "immediate_operand" ""))
		      (expr_list (match_operand 5 "register_operand" "") (match_operand 6 "immediate_operand" ""))])
		  (call (match_operand:SI 1 "" "")
			(match_operand 2 "" "")))
	     (clobber (reg:SI 15))])]
  ""
  "* return mcore_output_call (operands, 1);"
)


;; ------------------------------------------------------------------------
;; Misc insns
;; ------------------------------------------------------------------------

(define_insn "nop"
  [(const_int 0)]
  ""
  "or	r0,r0")

(define_insn "tablejump"
  [(set (pc)
	(match_operand:SI 0 "mcore_arith_reg_operand" "r"))
   (use (label_ref (match_operand 1 "" "")))]
  ""
  "jmp	%0"
  [(set_attr "type" "jmp")])

(define_insn "*return"
 [(return)]
 "reload_completed && ! mcore_naked_function_p ()"
 "jmp	r15"
 [(set_attr "type" "jmp")])

(define_insn "*no_return"
 [(return)]
 "reload_completed && mcore_naked_function_p ()"
 ""
 [(set_attr "length" "0")]
)

(define_expand "prologue"
  [(const_int 0)]
  ""
  "mcore_expand_prolog (); DONE;")

(define_expand "epilogue"
  [(return)]
  ""
  "mcore_expand_epilog ();")

;; ------------------------------------------------------------------------
;; Scc instructions
;; ------------------------------------------------------------------------

(define_insn "mvc"
  [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
	(ne:SI (reg:CC 17) (const_int 0)))]
  ""
  "mvc	%0"
  [(set_attr "type" "move")])

(define_insn "mvcv"
  [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
	(eq:SI (reg:CC 17) (const_int 0)))]
  ""
  "mvcv	%0"
  [(set_attr "type" "move")])

; in 0.97 use (LE 0) with (LT 1) and complement c.  BRC
(define_split 
  [(parallel[
     (set (match_operand:SI 0 "mcore_arith_reg_operand" "")
          (ne:SI (gt:CC (match_operand:SI 1 "mcore_arith_reg_operand" "")
                        (const_int 0))
                 (const_int 0)))
     (clobber (reg:SI 17))])]
  ""
  [(set (reg:CC 17)
        (lt:CC (match_dup 1) (const_int 1)))
   (set (match_dup 0) (eq:SI (reg:CC 17) (const_int 0)))])
     

(define_expand "seq"
  [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
	(eq:SI (match_dup 1) (const_int 0)))]
  ""
  "
{
  operands[1] = mcore_gen_compare_reg (NE);
}")

(define_expand "sne"
  [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
	(ne:SI (match_dup 1) (const_int 0)))]
  ""
  "
{
  operands[1] = mcore_gen_compare_reg (NE);
}")

(define_expand "slt"
  [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
	(ne:SI (match_dup 1) (const_int 0)))]
  ""
  "
{
  operands[1] = mcore_gen_compare_reg (LT);
}")

; make generating a LT with the comparison reversed easy.  BRC
(define_expand "reverse_slt"
  [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
        (eq:SI (match_dup 1) (const_int 0)))]
  ""
  "
{
  operands[1] = mcore_gen_compare_reg (LT);
}")

(define_expand "sge"
  [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
	(eq:SI (match_dup 1) (const_int 0)))]
  ""
  "
{
  operands[1] = mcore_gen_compare_reg (LT);
}")

; check whether (GT A imm) can become (LE A imm) with the comparison
; reversed.  if so, emit a (LT A imm + 1) in place of the (LE A imm).  BRC

(define_expand "sgt"
  [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
	(ne:SI (match_dup 1) (const_int 0)))]
  ""
  "
{
  if (mcore_modify_comparison (LE))
    {
      emit_insn (gen_reverse_slt (operands[0]));
      DONE;
    }
  
  operands[1] = mcore_gen_compare_reg (GT);
}")

(define_expand "sle"
  [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
	(eq:SI (match_dup 1) (const_int 0)))]
  ""
  "
{
  if (mcore_modify_comparison (LE))
    {
      emit_insn (gen_slt (operands[0]));
      DONE;
    }
  operands[1] = mcore_gen_compare_reg (GT);
}")

(define_expand "sltu"
  [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
	(eq:SI (match_dup 1) (const_int 0)))]
  ""
  "
{
  operands[1] = mcore_gen_compare_reg (GEU);
}")

(define_expand "sgeu"
  [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
	(ne:SI (match_dup 1) (const_int 0)))]
  ""
  "
{
  operands[1] = mcore_gen_compare_reg (GEU);
}")

(define_expand "sgtu"
  [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
	(eq:SI (match_dup 1) (const_int 0)))]
  ""
  "
{
  operands[1] = mcore_gen_compare_reg (LEU);
}")

(define_expand "sleu"
  [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
	(ne:SI (match_dup 1) (const_int 0)))]
  ""
  "
{
  operands[1] = mcore_gen_compare_reg (LEU);
}")

(define_insn "incscc"
  [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
	(plus:SI (ne (reg:CC 17) (const_int 0))
		 (match_operand:SI 1 "mcore_arith_reg_operand" "0")))]
  ""
  "inct	%0")

(define_insn "incscc_false"
  [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
	(plus:SI (eq (reg:CC 17) (const_int 0))
		 (match_operand:SI 1 "mcore_arith_reg_operand" "0")))]
  ""
  "incf	%0")

(define_insn "decscc"
  [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
	(minus:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0")
		  (ne (reg:CC 17) (const_int 0))))]
  ""
  "dect	%0")

(define_insn "decscc_false"
  [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
	(minus:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0")
		  (eq (reg:CC 17) (const_int 0))))]
  ""
  "decf	%0")

;; ------------------------------------------------------------------------
;; Conditional move patterns.
;; ------------------------------------------------------------------------

(define_expand "smaxsi3"
  [(set (reg:CC 17)
	(lt:CC (match_operand:SI 1 "mcore_arith_reg_operand" "")
	       (match_operand:SI 2 "mcore_arith_reg_operand" "")))
   (set (match_operand:SI 0 "mcore_arith_reg_operand" "")
	(if_then_else:SI (eq (reg:CC 17) (const_int 0))
			 (match_dup 1) (match_dup 2)))]
  ""
  "")
	       
(define_split
  [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
	(smax:SI (match_operand:SI 1 "mcore_arith_reg_operand" "")
		 (match_operand:SI 2 "mcore_arith_reg_operand" "")))]
  ""
  [(set (reg:CC 17)
	(lt:SI (match_dup 1) (match_dup 2)))
   (set (match_dup 0)
	(if_then_else:SI (eq (reg:CC 17) (const_int 0))
			 (match_dup 1) (match_dup 2)))]
  "")

; no tstgt in 0.97, so just use cmplti (btsti x,31) and reverse move 
; condition  BRC
(define_split
  [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
        (smax:SI (match_operand:SI 1 "mcore_arith_reg_operand" "")
                 (const_int 0)))]
  ""
  [(set (reg:CC 17)
        (lt:CC (match_dup 1) (const_int 0)))
   (set (match_dup 0)
        (if_then_else:SI (eq (reg:CC 17) (const_int 0))
                         (match_dup 1) (const_int 0)))]
  "")

(define_expand "sminsi3"
  [(set (reg:CC 17)
	(lt:CC (match_operand:SI 1 "mcore_arith_reg_operand" "")
	       (match_operand:SI 2 "mcore_arith_reg_operand" "")))
   (set (match_operand:SI 0 "mcore_arith_reg_operand" "")
	(if_then_else:SI (ne (reg:CC 17) (const_int 0))
			 (match_dup 1) (match_dup 2)))]
  ""
  "")

(define_split
  [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
	(smin:SI (match_operand:SI 1 "mcore_arith_reg_operand" "")
		 (match_operand:SI 2 "mcore_arith_reg_operand" "")))]
  ""
  [(set (reg:CC 17)
	(lt:SI (match_dup 1) (match_dup 2)))
   (set (match_dup 0)
	(if_then_else:SI (ne (reg:CC 17) (const_int 0))
			 (match_dup 1) (match_dup 2)))]
  "")

;(define_split
;  [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
;        (smin:SI (match_operand:SI 1 "mcore_arith_reg_operand" "")
;                 (const_int 0)))]
;  ""
;  [(set (reg:CC 17)
;        (gt:CC (match_dup 1) (const_int 0)))
;   (set (match_dup 0)
;        (if_then_else:SI (eq (reg:CC 17) (const_int 0))
;                         (match_dup 1) (const_int 0)))]
;  "")

; changed these unsigned patterns to use geu instead of ltu.  it appears
; that the c-torture & ssrl test suites didn't catch these!  only showed
; up in friedman's clib work.   BRC 7/7/95

(define_expand "umaxsi3"
  [(set (reg:CC 17)
	(geu:CC (match_operand:SI 1 "mcore_arith_reg_operand" "")
		(match_operand:SI 2 "mcore_arith_reg_operand" "")))
   (set (match_operand:SI 0 "mcore_arith_reg_operand" "")
	(if_then_else:SI (eq (reg:CC 17) (const_int 0))
			 (match_dup 2) (match_dup 1)))]
  ""
  "")
	       
(define_split
  [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
	(umax:SI (match_operand:SI 1 "mcore_arith_reg_operand" "")
		 (match_operand:SI 2 "mcore_arith_reg_operand" "")))]
  ""
  [(set (reg:CC 17)
	(geu:SI (match_dup 1) (match_dup 2)))
   (set (match_dup 0)
	(if_then_else:SI (eq (reg:CC 17) (const_int 0))
			 (match_dup 2) (match_dup 1)))]
  "")

(define_expand "uminsi3"
  [(set (reg:CC 17)
	(geu:CC (match_operand:SI 1 "mcore_arith_reg_operand" "")
		(match_operand:SI 2 "mcore_arith_reg_operand" "")))
   (set (match_operand:SI 0 "mcore_arith_reg_operand" "")
	(if_then_else:SI (ne (reg:CC 17) (const_int 0))
			 (match_dup 2) (match_dup 1)))]
  ""
  "")

(define_split
  [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
	(umin:SI (match_operand:SI 1 "mcore_arith_reg_operand" "")
		 (match_operand:SI 2 "mcore_arith_reg_operand" "")))]
  ""
  [(set (reg:CC 17)
	(geu:SI (match_dup 1) (match_dup 2)))
   (set (match_dup 0)
	(if_then_else:SI (ne (reg:CC 17) (const_int 0))
			 (match_dup 2) (match_dup 1)))]
  "")

;; ------------------------------------------------------------------------
;; conditional move patterns really start here
;; ------------------------------------------------------------------------

;; the "movtK" patterns are experimental.  they are intended to account for
;; gcc's mucking on code such as:
;;
;;            free_ent = ((block_compress) ? 257 : 256 );
;;
;; these patterns help to get a tstne/bgeni/inct (or equivalent) sequence
;; when both arms have constants that are +/- 1 of each other.
;;
;; note in the following patterns that the "movtK" ones should be the first
;; one defined in each sequence.  this is because the general pattern also
;; matches, so use ordering to determine priority (it's easier this way than
;; adding conditions to the general patterns).   BRC
;;
;; the U and Q constraints are necessary to ensure that reload does the
;; 'right thing'.  U constrains the operand to 0 and Q to 1 for use in the
;; clrt & clrf and clrt/inct & clrf/incf patterns.    BRC 6/26
;;
;; ??? there appears to be some problems with these movtK patterns for ops
;; other than eq & ne.  need to fix.  6/30 BRC

;; ------------------------------------------------------------------------
;; ne 
;; ------------------------------------------------------------------------

; experimental conditional move with t