mcore.md

linux下的gcc编译器

                  (match_operand:SI 2 "mcore_arith_reg_operand" "0")))]
  ""
  "rsubi	%0,%1")

(define_insn "adddi3"
  [(set (match_operand:DI 0 "mcore_arith_reg_operand" "=&r")
	(plus:DI (match_operand:DI 1 "mcore_arith_reg_operand" "%0")
		 (match_operand:DI 2 "mcore_arith_reg_operand" "r")))
   (clobber (reg:CC 17))]
  ""
  "*
  {
    if (TARGET_LITTLE_END)
      return \"cmplt	%0,%0\;addc	%0,%2\;addc	%R0,%R2\";
    return \"cmplt	%R0,%R0\;addc	%R0,%R2\;addc	%0,%2\";
  }"
  [(set_attr "length" "6")])

;; special case for "longlong += 1"
(define_insn ""
  [(set (match_operand:DI 0 "mcore_arith_reg_operand" "=&r")
	(plus:DI (match_operand:DI 1 "mcore_arith_reg_operand" "0")
		 (const_int 1)))
   (clobber (reg:CC 17))]
  ""
  "*
  {
   if (TARGET_LITTLE_END)
      return \"addi	%0,1\;cmpnei %0,0\;incf	%R0\";
    return \"addi	%R0,1\;cmpnei %R0,0\;incf	%0\";
  }"
  [(set_attr "length" "6")])

;; special case for "longlong -= 1"
(define_insn ""
  [(set (match_operand:DI 0 "mcore_arith_reg_operand" "=&r")
	(plus:DI (match_operand:DI 1 "mcore_arith_reg_operand" "0")
		 (const_int -1)))
   (clobber (reg:CC 17))]
  ""
  "*
  {
    if (TARGET_LITTLE_END)
       return \"cmpnei %0,0\;decf	%R0\;subi	%0,1\";
    return \"cmpnei %R0,0\;decf	%0\;subi	%R0,1\";
  }"
  [(set_attr "length" "6")])

;; special case for "longlong += const_int"
;; we have to use a register for the const_int because we don't
;; have an unsigned compare immediate... only +/- 1 get to
;; play the no-extra register game because they compare with 0.
;; This winds up working out for any literal that is synthesized
;; with a single instruction. The more complicated ones look
;; like the get broken into subreg's to get initialized too soon
;; for us to catch here. -- RBE 4/25/96
;; only allow for-sure positive values.

(define_insn ""
  [(set (match_operand:DI 0 "mcore_arith_reg_operand" "=&r")
	(plus:DI (match_operand:DI 1 "mcore_arith_reg_operand" "0")
		 (match_operand:SI 2 "const_int_operand" "r")))
   (clobber (reg:CC 17))]
  "GET_CODE (operands[2]) == CONST_INT
   && INTVAL (operands[2]) > 0 && ! (INTVAL (operands[2]) & 0x80000000)"
  "*
{
  if (GET_MODE (operands[2]) != SImode)
     abort ();
  if (TARGET_LITTLE_END)
    return \"addu	%0,%2\;cmphs	%0,%2\;incf	%R0\";
  return \"addu	%R0,%2\;cmphs	%R0,%2\;incf	%0\";
}"
  [(set_attr "length" "6")])

;; optimize "long long" + "unsigned long"
;; won't trigger because of how the extension is expanded upstream.
;; (define_insn ""
;;   [(set (match_operand:DI 0 "mcore_arith_reg_operand" "=&r")
;; 	(plus:DI (match_operand:DI 1 "mcore_arith_reg_operand" "%0")
;; 		 (zero_extend:DI (match_operand:SI 2 "mcore_arith_reg_operand" "r"))))
;;    (clobber (reg:CC 17))]
;;   "0"
;;   "cmplt	%R0,%R0\;addc	%R0,%2\;inct	%0"
;;   [(set_attr "length" "6")])

;; optimize "long long" + "signed long"
;; won't trigger because of how the extension is expanded upstream.
;; (define_insn ""
;;   [(set (match_operand:DI 0 "mcore_arith_reg_operand" "=&r")
;; 	(plus:DI (match_operand:DI 1 "mcore_arith_reg_operand" "%0")
;; 		 (sign_extend:DI (match_operand:SI 2 "mcore_arith_reg_operand" "r"))))
;;    (clobber (reg:CC 17))]
;;   "0"
;;   "cmplt	%R0,%R0\;addc	%R0,%2\;inct	%0\;btsti	%2,31\;dect	%0"
;;   [(set_attr "length" "6")])

(define_insn "subdi3"
  [(set (match_operand:DI 0 "mcore_arith_reg_operand" "=&r")
	(minus:DI (match_operand:DI 1 "mcore_arith_reg_operand" "0")
		  (match_operand:DI 2 "mcore_arith_reg_operand" "r")))
   (clobber (reg:CC 17))]
  ""
  "*
  {
    if (TARGET_LITTLE_END)
      return \"cmphs	%0,%0\;subc	%0,%2\;subc	%R0,%R2\";
    return \"cmphs	%R0,%R0\;subc	%R0,%R2\;subc	%0,%2\";
  }"
  [(set_attr "length" "6")])

;; -------------------------------------------------------------------------
;; Multiplication instructions
;; -------------------------------------------------------------------------

(define_insn "mulsi3"
  [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
	(mult:SI (match_operand:SI 1 "mcore_arith_reg_operand" "%0")
		 (match_operand:SI 2 "mcore_arith_reg_operand" "r")))]
  ""
  "mult	%0,%2")

;;
;; 32/32 signed division -- added to the MCORE instruction set spring 1997
;;
;; Different constraints based on the architecture revision...
;;
(define_expand "divsi3"
  [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
        (div:SI (match_operand:SI 1 "mcore_arith_reg_operand" "")
                (match_operand:SI 2 "mcore_arith_reg_operand" "")))]
  "TARGET_DIV"
  "")
 
;; MCORE Revision 1.50: restricts the divisor to be in r1. (6/97)
;;
(define_insn ""
  [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
        (div:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0")
                (match_operand:SI 2 "mcore_arith_reg_operand" "b")))]
  "TARGET_DIV"
  "divs %0,%2")

;;
;; 32/32 signed division -- added to the MCORE instruction set spring 1997
;;
;; Different constraints based on the architecture revision...
;;
(define_expand "udivsi3"
  [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
        (udiv:SI (match_operand:SI 1 "mcore_arith_reg_operand" "")
                 (match_operand:SI 2 "mcore_arith_reg_operand" "")))]
  "TARGET_DIV"
  "")
 
;; MCORE Revision 1.50: restricts the divisor to be in r1. (6/97)
(define_insn ""
  [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
        (udiv:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0")
                 (match_operand:SI 2 "mcore_arith_reg_operand" "b")))]
  "TARGET_DIV"
  "divu %0,%2")
 
;; -------------------------------------------------------------------------
;; Unary arithmetic
;; -------------------------------------------------------------------------

(define_insn "negsi2"
  [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
	(neg:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0")))]
  ""
  "*
{
   return \"rsubi	%0,0\";
}")


(define_insn "abssi2"
  [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
	(abs:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0")))]
  ""
  "abs	%0")
	     
(define_insn "negdi2"
  [(set (match_operand:DI 0 "mcore_arith_reg_operand" "=&r")
	(neg:DI (match_operand:DI 1 "mcore_arith_reg_operand" "0")))
   (clobber (reg:CC 17))]
  ""
  "*
{
   if (TARGET_LITTLE_END)
     return \"cmpnei	%0,0\\n\\trsubi	%0,0\\n\\tnot	%R0\\n\\tincf	%R0\";
   return \"cmpnei	%R0,0\\n\\trsubi	%R0,0\\n\\tnot	%0\\n\\tincf	%0\";
}"
  [(set_attr "length" "8")])

(define_insn "one_cmplsi2"
  [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
	(not:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0")))]
  ""
  "not	%0")

;; -------------------------------------------------------------------------
;; Zero extension instructions
;; -------------------------------------------------------------------------

(define_expand "zero_extendhisi2"
  [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
	(zero_extend:SI (match_operand:HI 1 "mcore_arith_reg_operand" "")))]
  ""
  "")

(define_insn ""
  [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r")
	(zero_extend:SI (match_operand:HI 1 "general_operand" "0,m")))]
  ""
  "@
	zexth	%0
	ld.h	%0,%1"
  [(set_attr "type" "shift,load")])

;; ldh gives us a free zero-extension. The combiner picks up on this.
(define_insn ""
  [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
	(zero_extend:SI (mem:HI (match_operand:SI 1 "mcore_arith_reg_operand" "r"))))]
  ""
  "ld.h	%0,(%1)"
  [(set_attr "type" "load")])

(define_insn ""
  [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
	(zero_extend:SI (mem:HI (plus:SI (match_operand:SI 1 "mcore_arith_reg_operand" "r")
				         (match_operand:SI 2 "const_int_operand" "")))))]
  "(INTVAL (operands[2]) >= 0) &&
   (INTVAL (operands[2]) < 32) &&
   ((INTVAL (operands[2])&1) == 0)"
  "ld.h	%0,(%1,%2)"
  [(set_attr "type" "load")])

(define_expand "zero_extendqisi2"
  [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
	(zero_extend:SI (match_operand:QI 1 "general_operand" "")))]
  ""
  "") 

;; RBE: XXX: we don't recognize that the xtrb3 kills the CC register.
(define_insn ""
  [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,b,r")
	(zero_extend:SI (match_operand:QI 1 "general_operand" "0,r,m")))]
  ""
  "@
	zextb	%0
	xtrb3	%0,%1
	ld.b	%0,%1"
  [(set_attr "type" "shift,shift,load")])

;; ldb gives us a free zero-extension. The combiner picks up on this.
(define_insn ""
  [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
	(zero_extend:SI (mem:QI (match_operand:SI 1 "mcore_arith_reg_operand" "r"))))]
  ""
  "ld.b	%0,(%1)"
  [(set_attr "type" "load")])

(define_insn ""
  [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
	(zero_extend:SI (mem:QI (plus:SI (match_operand:SI 1 "mcore_arith_reg_operand" "r")
				         (match_operand:SI 2 "const_int_operand" "")))))]
  "(INTVAL (operands[2]) >= 0) &&
   (INTVAL (operands[2]) < 16)"
  "ld.b	%0,(%1,%2)"
  [(set_attr "type" "load")])

(define_expand "zero_extendqihi2"
  [(set (match_operand:HI 0 "mcore_arith_reg_operand" "")
	(zero_extend:HI (match_operand:QI 1 "general_operand" "")))]
  ""
  "") 

;; RBE: XXX: we don't recognize that the xtrb3 kills the CC register.
(define_insn ""
  [(set (match_operand:HI 0 "mcore_arith_reg_operand" "=r,b,r")
	(zero_extend:HI (match_operand:QI 1 "general_operand" "0,r,m")))]
  ""
  "@
	zextb	%0
	xtrb3	%0,%1
	ld.b	%0,%1"
  [(set_attr "type" "shift,shift,load")])

;; ldb gives us a free zero-extension. The combiner picks up on this.
;; this doesn't catch references that are into a structure.
;; note that normally the compiler uses the above insn, unless it turns
;; out that we're dealing with a volatile...
(define_insn ""
  [(set (match_operand:HI 0 "mcore_arith_reg_operand" "=r")
	(zero_extend:HI (mem:QI (match_operand:SI 1 "mcore_arith_reg_operand" "r"))))]
  ""
  "ld.b	%0,(%1)"
  [(set_attr "type" "load")])

(define_insn ""
  [(set (match_operand:HI 0 "mcore_arith_reg_operand" "=r")
	(zero_extend:HI (mem:QI (plus:SI (match_operand:SI 1 "mcore_arith_reg_operand" "r")
				         (match_operand:SI 2 "const_int_operand" "")))))]
  "(INTVAL (operands[2]) >= 0) &&
   (INTVAL (operands[2]) < 16)"
  "ld.b	%0,(%1,%2)"
  [(set_attr "type" "load")])


;; -------------------------------------------------------------------------
;; Sign extension instructions
;; -------------------------------------------------------------------------

(define_expand "extendsidi2"
  [(set (match_operand:DI 0 "mcore_arith_reg_operand" "=r") 
	(match_operand:SI 1 "mcore_arith_reg_operand" "r"))]
  ""
  "
  {
    int low, high;

    if (TARGET_LITTLE_END)
      low = 0, high = 4;
    else
      low = 4, high = 0;
    
    emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], low),
	      operands[1]));
    emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], high),
	      gen_rtx_ASHIFTRT (SImode,
			       gen_rtx_SUBREG (SImode, operands[0], low),
			       GEN_INT (31))));
    DONE;
  }"
)

(define_insn "extendhisi2"
  [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
	(sign_extend:SI (match_operand:HI 1 "mcore_arith_reg_operand" "0")))]
  ""
  "sexth	%0")

(define_insn "extendqisi2"
  [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
	(sign_extend:SI (match_operand:QI 1 "mcore_arith_reg_operand" "0")))]
  ""
  "sextb	%0")

(define_insn "extendqihi2"
  [(set (match_operand:HI 0 "mcore_arith_reg_operand" "=r")
	(sign_extend:HI (match_operand:QI 1 "mcore_arith_reg_operand" "0")))]
  ""
  "sextb	%0")

;; -------------------------------------------------------------------------
;; Move instructions
;; -------------------------------------------------------------------------

;; SImode

(define_expand "movsi"
  [(set (match_operand:SI 0 "general_operand" "")
	(match_operand:SI 1 "general_operand" ""))]
  ""
  "
{
  if (GET_CODE (operands[0]) == MEM)
    operands[1] = force_reg (SImode, operands[1]);
}")

(define_insn ""
  [(set (match_operand:SI 0 "mcore_general_movdst_operand" "=r,r,a,r,a,r,m")
	(match_operand:SI 1 "mcore_general_movsrc_operand"  "r,P,i,c,R,m,r"))]
  "(register_operand (operands[0], SImode)
    || register_operand (operands[1], SImode))"
  "* return mcore_output_move (insn, operands, SImode);"
  [(set_attr "type" "move,move,move,move,load,load,store")])

;;
;; HImode
;;

(define_expand "movhi"
  [(set (match_operand:HI 0 "general_operand" "")
	(match_operand:HI 1 "general_operand"  ""))]
  ""
  "
{
  if (GET_CODE (operands[0]) == MEM)
    operands[1] = force_reg (HImode, operands[1]);
  else if (CONSTANT_P (operands[1])
	   && (GET_CODE (operands[1]) != CONST_INT
	       || (! CONST_OK_FOR_I (INTVAL (operands[1]))
		   && ! CONST_OK_FOR_M (INTVAL (operands[1]))
		   && ! CONST_OK_FOR_N (INTVAL (operands[1]))))
	   && ! reload_completed && ! reload_in_progress)
    {
      rtx reg = gen_reg_rtx (SImode);
      emit_insn (gen_movsi (reg, operands[1]));
      operands[1] = gen_lowpart (HImode, reg);
    }
}")
  
(define_insn ""
  [(set (match_operand:HI 0 "mcore_general_movdst_operand" "=r,r,a,r,r,m")
	(match_operand:HI 1 "mcore_general_movsrc_operand"  "r,P,i,c,m,r"))]
  "(register_operand (operands[0], HImode)
    || register_operand (operands[1], HImode))"
  "* return mcore_output_move (insn, operands, HImode);"
  [(set_attr "type" "move,move,move,move,load,store")])

;;
;; QImode
;;

(define_expand "movqi"
  [(set (match_operand:QI 0 "general_operand" "")
	(match_operand:QI 1 "general_operand"  ""))]
  ""
  "
{
  if (GET_CODE (operands[0]) == MEM)
    operands[1] = force_reg (QImode, operands[1]);
  else if (CONSTANT_P (operands[1])
	   && (GET_CODE (operands[1]) != CONST_INT
	       || (! CONST_OK_FOR_I (INTVAL (operands[1]))
		   && ! CONST_OK_FOR_M (INTVAL (operands[1]))