📄 xtensa.h
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/* Definitions of Tensilica's Xtensa target machine for GNU compiler. Copyright 2001, 2002, 2003, 2004 Free Software Foundation, Inc. Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica.This file is part of GCC.GCC is free software; you can redistribute it and/or modify it underthe terms of the GNU General Public License as published by the FreeSoftware Foundation; either version 2, or (at your option) any laterversion.GCC is distributed in the hope that it will be useful, but WITHOUT ANYWARRANTY; without even the implied warranty of MERCHANTABILITY orFITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public Licensefor more details.You should have received a copy of the GNU General Public Licensealong with GCC; see the file COPYING. If not, write to the FreeSoftware Foundation, 59 Temple Place - Suite 330, Boston, MA02111-1307, USA. *//* Get Xtensa configuration settings */#include "xtensa/xtensa-config.h"/* Standard GCC variables that we reference. */extern int current_function_calls_alloca;extern int target_flags;extern int optimize;/* External variables defined in xtensa.c. *//* comparison type */enum cmp_type { CMP_SI, /* four byte integers */ CMP_DI, /* eight byte integers */ CMP_SF, /* single precision floats */ CMP_DF, /* double precision floats */ CMP_MAX /* max comparison type */};extern struct rtx_def * branch_cmp[2]; /* operands for compare */extern enum cmp_type branch_type; /* what type of branch to use */extern unsigned xtensa_current_frame_size;/* Run-time compilation parameters selecting different hardware subsets. */#define MASK_BIG_ENDIAN 0x00000001 /* big or little endian */#define MASK_DENSITY 0x00000002 /* code density option */#define MASK_MAC16 0x00000004 /* MAC16 option */#define MASK_MUL16 0x00000008 /* 16-bit integer multiply */#define MASK_MUL32 0x00000010 /* integer multiply/divide */#define MASK_DIV32 0x00000020 /* integer multiply/divide */#define MASK_NSA 0x00000040 /* nsa instruction option */#define MASK_MINMAX 0x00000080 /* min/max instructions */#define MASK_SEXT 0x00000100 /* sign extend insn option */#define MASK_BOOLEANS 0x00000200 /* boolean register option */#define MASK_HARD_FLOAT 0x00000400 /* floating-point option */#define MASK_HARD_FLOAT_DIV 0x00000800 /* floating-point divide */#define MASK_HARD_FLOAT_RECIP 0x00001000 /* floating-point reciprocal */#define MASK_HARD_FLOAT_SQRT 0x00002000 /* floating-point sqrt */#define MASK_HARD_FLOAT_RSQRT 0x00004000 /* floating-point recip sqrt */#define MASK_NO_FUSED_MADD 0x00008000 /* avoid f-p mul/add */#define MASK_SERIALIZE_VOLATILE 0x00010000 /* serialize volatile refs *//* Macros used in the machine description to test the flags. */#define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)#define TARGET_DENSITY (target_flags & MASK_DENSITY)#define TARGET_MAC16 (target_flags & MASK_MAC16)#define TARGET_MUL16 (target_flags & MASK_MUL16)#define TARGET_MUL32 (target_flags & MASK_MUL32)#define TARGET_DIV32 (target_flags & MASK_DIV32)#define TARGET_NSA (target_flags & MASK_NSA)#define TARGET_MINMAX (target_flags & MASK_MINMAX)#define TARGET_SEXT (target_flags & MASK_SEXT)#define TARGET_BOOLEANS (target_flags & MASK_BOOLEANS)#define TARGET_HARD_FLOAT (target_flags & MASK_HARD_FLOAT)#define TARGET_HARD_FLOAT_DIV (target_flags & MASK_HARD_FLOAT_DIV)#define TARGET_HARD_FLOAT_RECIP (target_flags & MASK_HARD_FLOAT_RECIP)#define TARGET_HARD_FLOAT_SQRT (target_flags & MASK_HARD_FLOAT_SQRT)#define TARGET_HARD_FLOAT_RSQRT (target_flags & MASK_HARD_FLOAT_RSQRT)#define TARGET_NO_FUSED_MADD (target_flags & MASK_NO_FUSED_MADD)#define TARGET_SERIALIZE_VOLATILE (target_flags & MASK_SERIALIZE_VOLATILE)/* Default target_flags if no switches are specified */#define TARGET_DEFAULT ( \ (XCHAL_HAVE_BE ? MASK_BIG_ENDIAN : 0) | \ (XCHAL_HAVE_DENSITY ? MASK_DENSITY : 0) | \ (XCHAL_HAVE_MAC16 ? MASK_MAC16 : 0) | \ (XCHAL_HAVE_MUL16 ? MASK_MUL16 : 0) | \ (XCHAL_HAVE_MUL32 ? MASK_MUL32 : 0) | \ (XCHAL_HAVE_DIV32 ? MASK_DIV32 : 0) | \ (XCHAL_HAVE_NSA ? MASK_NSA : 0) | \ (XCHAL_HAVE_MINMAX ? MASK_MINMAX : 0) | \ (XCHAL_HAVE_SEXT ? MASK_SEXT : 0) | \ (XCHAL_HAVE_BOOLEANS ? MASK_BOOLEANS : 0) | \ (XCHAL_HAVE_FP ? MASK_HARD_FLOAT : 0) | \ (XCHAL_HAVE_FP_DIV ? MASK_HARD_FLOAT_DIV : 0) | \ (XCHAL_HAVE_FP_RECIP ? MASK_HARD_FLOAT_RECIP : 0) | \ (XCHAL_HAVE_FP_SQRT ? MASK_HARD_FLOAT_SQRT : 0) | \ (XCHAL_HAVE_FP_RSQRT ? MASK_HARD_FLOAT_RSQRT : 0) | \ MASK_SERIALIZE_VOLATILE)/* Macro to define tables used to set the flags. */#define TARGET_SWITCHES \{ \ {"big-endian", MASK_BIG_ENDIAN, \ N_("Use big-endian byte order")}, \ {"little-endian", -MASK_BIG_ENDIAN, \ N_("Use little-endian byte order")}, \ {"density", MASK_DENSITY, \ N_("Use the Xtensa code density option")}, \ {"no-density", -MASK_DENSITY, \ N_("Do not use the Xtensa code density option")}, \ {"mac16", MASK_MAC16, \ N_("Use the Xtensa MAC16 option")}, \ {"no-mac16", -MASK_MAC16, \ N_("Do not use the Xtensa MAC16 option")}, \ {"mul16", MASK_MUL16, \ N_("Use the Xtensa MUL16 option")}, \ {"no-mul16", -MASK_MUL16, \ N_("Do not use the Xtensa MUL16 option")}, \ {"mul32", MASK_MUL32, \ N_("Use the Xtensa MUL32 option")}, \ {"no-mul32", -MASK_MUL32, \ N_("Do not use the Xtensa MUL32 option")}, \ {"div32", MASK_DIV32, \ 0 /* undocumented */}, \ {"no-div32", -MASK_DIV32, \ 0 /* undocumented */}, \ {"nsa", MASK_NSA, \ N_("Use the Xtensa NSA option")}, \ {"no-nsa", -MASK_NSA, \ N_("Do not use the Xtensa NSA option")}, \ {"minmax", MASK_MINMAX, \ N_("Use the Xtensa MIN/MAX option")}, \ {"no-minmax", -MASK_MINMAX, \ N_("Do not use the Xtensa MIN/MAX option")}, \ {"sext", MASK_SEXT, \ N_("Use the Xtensa SEXT option")}, \ {"no-sext", -MASK_SEXT, \ N_("Do not use the Xtensa SEXT option")}, \ {"booleans", MASK_BOOLEANS, \ N_("Use the Xtensa boolean register option")}, \ {"no-booleans", -MASK_BOOLEANS, \ N_("Do not use the Xtensa boolean register option")}, \ {"hard-float", MASK_HARD_FLOAT, \ N_("Use the Xtensa floating-point unit")}, \ {"soft-float", -MASK_HARD_FLOAT, \ N_("Do not use the Xtensa floating-point unit")}, \ {"hard-float-div", MASK_HARD_FLOAT_DIV, \ 0 /* undocumented */}, \ {"no-hard-float-div", -MASK_HARD_FLOAT_DIV, \ 0 /* undocumented */}, \ {"hard-float-recip", MASK_HARD_FLOAT_RECIP, \ 0 /* undocumented */}, \ {"no-hard-float-recip", -MASK_HARD_FLOAT_RECIP, \ 0 /* undocumented */}, \ {"hard-float-sqrt", MASK_HARD_FLOAT_SQRT, \ 0 /* undocumented */}, \ {"no-hard-float-sqrt", -MASK_HARD_FLOAT_SQRT, \ 0 /* undocumented */}, \ {"hard-float-rsqrt", MASK_HARD_FLOAT_RSQRT, \ 0 /* undocumented */}, \ {"no-hard-float-rsqrt", -MASK_HARD_FLOAT_RSQRT, \ 0 /* undocumented */}, \ {"no-fused-madd", MASK_NO_FUSED_MADD, \ N_("Disable fused multiply/add and multiply/subtract FP instructions")}, \ {"fused-madd", -MASK_NO_FUSED_MADD, \ N_("Enable fused multiply/add and multiply/subtract FP instructions")}, \ {"serialize-volatile", MASK_SERIALIZE_VOLATILE, \ N_("Serialize volatile memory references with MEMW instructions")}, \ {"no-serialize-volatile", -MASK_SERIALIZE_VOLATILE, \ N_("Do not serialize volatile memory references with MEMW instructions")},\ {"text-section-literals", 0, \ N_("Intersperse literal pools with code in the text section")}, \ {"no-text-section-literals", 0, \ N_("Put literal pools in a separate literal section")}, \ {"target-align", 0, \ N_("Automatically align branch targets to reduce branch penalties")}, \ {"no-target-align", 0, \ N_("Do not automatically align branch targets")}, \ {"longcalls", 0, \ N_("Use indirect CALLXn instructions for large programs")}, \ {"no-longcalls", 0, \ N_("Use direct CALLn instructions for fast calls")}, \ {"", TARGET_DEFAULT, 0} \}#define OVERRIDE_OPTIONS override_options () /* Target CPU builtins. */#define TARGET_CPU_CPP_BUILTINS() \ do { \ builtin_assert ("cpu=xtensa"); \ builtin_assert ("machine=xtensa"); \ builtin_define ("__XTENSA__"); \ builtin_define (TARGET_BIG_ENDIAN ? "__XTENSA_EB__" : "__XTENSA_EL__"); \ if (!TARGET_HARD_FLOAT) \ builtin_define ("__XTENSA_SOFT_FLOAT__"); \ if (flag_pic) \ { \ builtin_define ("__PIC__"); \ builtin_define ("__pic__"); \ } \ } while (0)#define CPP_SPEC " %(subtarget_cpp_spec) "#ifndef SUBTARGET_CPP_SPEC#define SUBTARGET_CPP_SPEC ""#endif#define EXTRA_SPECS \ { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC },/* Define this to set the endianness to use in libgcc2.c, which can not depend on target_flags. */#define LIBGCC2_WORDS_BIG_ENDIAN XCHAL_HAVE_BE/* Show we can debug even without a frame pointer. */#define CAN_DEBUG_WITHOUT_FP/* Target machine storage layout *//* Define this if most significant bit is lowest numbered in instructions that operate on numbered bit-fields. */#define BITS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)/* Define this if most significant byte of a word is the lowest numbered. */#define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)/* Define this if most significant word of a multiword number is the lowest. */#define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)#define MAX_BITS_PER_WORD 32/* Width of a word, in units (bytes). */#define UNITS_PER_WORD 4#define MIN_UNITS_PER_WORD 4/* Width of a floating point register. */#define UNITS_PER_FPREG 4/* Size in bits of various types on the target machine. */#define INT_TYPE_SIZE 32#define SHORT_TYPE_SIZE 16#define LONG_TYPE_SIZE 32#define MAX_LONG_TYPE_SIZE 32#define LONG_LONG_TYPE_SIZE 64#define FLOAT_TYPE_SIZE 32#define DOUBLE_TYPE_SIZE 64#define LONG_DOUBLE_TYPE_SIZE 64/* Allocation boundary (in *bits*) for storing pointers in memory. */#define POINTER_BOUNDARY 32/* Allocation boundary (in *bits*) for storing arguments in argument list. */#define PARM_BOUNDARY 32/* Allocation boundary (in *bits*) for the code of a function. */#define FUNCTION_BOUNDARY 32/* Alignment of field after 'int : 0' in a structure. */#define EMPTY_FIELD_BOUNDARY 32/* Every structure's size must be a multiple of this. */#define STRUCTURE_SIZE_BOUNDARY 8/* There is no point aligning anything to a rounder boundary than this. */#define BIGGEST_ALIGNMENT 128/* Set this nonzero if move instructions will actually fail to work when given unaligned data. */#define STRICT_ALIGNMENT 1/* Promote integer modes smaller than a word to SImode. Set UNSIGNEDP for QImode, because there is no 8-bit load from memory with sign extension. Otherwise, leave UNSIGNEDP alone, since Xtensa has 16-bit loads both with and without sign extension. */#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ do { \ if (GET_MODE_CLASS (MODE) == MODE_INT \ && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ { \ if ((MODE) == QImode) \ (UNSIGNEDP) = 1; \ (MODE) = SImode; \ } \ } while (0)/* The promotion described by `PROMOTE_MODE' should also be done for outgoing function arguments. */#define PROMOTE_FUNCTION_ARGS/* The promotion described by `PROMOTE_MODE' should also be done for the return value of functions. Note: `FUNCTION_VALUE' must perform the same promotions done by `PROMOTE_MODE'. */#define PROMOTE_FUNCTION_RETURN/* Imitate the way many other C compilers handle alignment of bitfields and the structures that contain them. */#define PCC_BITFIELD_TYPE_MATTERS 1/* Align string constants and constructors to at least a word boundary. The typical use of this macro is to increase alignment for string constants to be word aligned so that 'strcpy' calls that copy constants can be done inline. */#define CONSTANT_ALIGNMENT(EXP, ALIGN) \ ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \ && (ALIGN) < BITS_PER_WORD \ ? BITS_PER_WORD \ : (ALIGN))/* Align arrays, unions and records to at least a word boundary. One use of this macro is to increase alignment of medium-size data to make it all fit in fewer cache lines. Another is to cause character arrays to be word-aligned so that 'strcpy' calls that copy constants to character arrays can be done inline. */#undef DATA_ALIGNMENT#define DATA_ALIGNMENT(TYPE, ALIGN) \ ((((ALIGN) < BITS_PER_WORD) \ && (TREE_CODE (TYPE) == ARRAY_TYPE \ || TREE_CODE (TYPE) == UNION_TYPE \ || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))⌨️ 快捷键说明
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