d30v.c

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      if (GET_MODE (op) != mode && mode != VOIDmode)
        return FALSE;

      subreg = SUBREG_REG (op);
      code = GET_CODE (subreg);
      if (code == MEM)
	return d30v_legitimate_address_p ((int)mode, XEXP (subreg, 0),
					  reload_completed);

      return (code == REG);

    case REG:
      if (GET_MODE (op) != mode && mode != VOIDmode)
	return FALSE;

      return TRUE;

    case MEM:
      if (GET_CODE (XEXP (op, 0)) == ADDRESSOF)
	return TRUE;
      return d30v_legitimate_address_p (mode, XEXP (op, 0),
					reload_completed);
    }

  return FALSE;
}

/* Return true if operand is a signed 6 bit immediate.  */

int
signed6_operand (op, mode)
     rtx op;
     enum machine_mode mode ATTRIBUTE_UNUSED;
{
  if (GET_CODE (op) == CONST_INT)
    return IN_RANGE_P (INTVAL (op), -32, 31);

  return FALSE;
}

/* Return true if operand is an unsigned 5 bit immediate.  */

int
unsigned5_operand (op, mode)
     rtx op;
     enum machine_mode mode ATTRIBUTE_UNUSED;
{
  if (GET_CODE (op) == CONST_INT)
    return IN_RANGE_P (INTVAL (op), 0, 31);

  return FALSE;
}

/* Return true if operand is an unsigned 6 bit immediate.  */

int
unsigned6_operand (op, mode)
     rtx op;
     enum machine_mode mode ATTRIBUTE_UNUSED;
{
  if (GET_CODE (op) == CONST_INT)
    return IN_RANGE_P (INTVAL (op), 0, 63);

  return FALSE;
}

/* Return true if operand is a constant with a single bit set.  */

int
bitset_operand (op, mode)
     rtx op;
     enum machine_mode mode ATTRIBUTE_UNUSED;
{
  if (GET_CODE (op) == CONST_INT)
    return IN_RANGE_P (exact_log2 (INTVAL (op)), 0, 31);

  return FALSE;
}

/* Return true if the operator is a ==/!= test against f0 or f1 that can be
   used in conditional execution.  */

int
condexec_test_operator (op, mode)
     rtx op;
     enum machine_mode mode;
{
  rtx x0, x1;

  if (GET_MODE (op) != mode && mode != VOIDmode)
    return FALSE;

  if (GET_CODE (op) != EQ && GET_CODE (op) != NE)
    return FALSE;

  x0 = XEXP (op, 0);
  if (GET_CODE (x0) != REG || !BR_FLAG_OR_PSEUDO_P (REGNO (x0)))
    return FALSE;

  x1 = XEXP (op, 1);
  if (GET_CODE (x1) != CONST_INT || INTVAL (x1) != 0)
    return FALSE;

  return TRUE;
}

/* Return true if the operator is a ==/!= test against f0, f1, or a general
   register that can be used in a branch instruction.  */

int
condexec_branch_operator (op, mode)
     rtx op;
     enum machine_mode mode;
{
  rtx x0, x1;

  if (GET_MODE (op) != mode && mode != VOIDmode)
    return FALSE;

  if (GET_CODE (op) != EQ && GET_CODE (op) != NE)
    return FALSE;

  x0 = XEXP (op, 0);
  if (GET_CODE (x0) == REG)
    {
      int regno = REGNO (x0);
      if (!GPR_OR_PSEUDO_P (regno) && !BR_FLAG_P (regno))
	return FALSE;
    }
  /* Allow the optimizer to generate things like:
     (if_then_else (ne (const_int 1) (const_int 0))) */
  else if (GET_CODE (x0) != CONST_INT)
    return FALSE;

  x1 = XEXP (op, 1);
  if (GET_CODE (x1) != CONST_INT || INTVAL (x1) != 0)
    return FALSE;

  return TRUE;
}

/* Return true if the unary operator can be executed with conditional
   execution.  */

int
condexec_unary_operator (op, mode)
     rtx op;
     enum machine_mode mode ATTRIBUTE_UNUSED;
{
  rtx op0;

  /* Only do this after register allocation, so that we can look at the register # */
  if (!reload_completed)
    return FALSE;

  if (GET_RTX_CLASS (GET_CODE (op)) != '1')
    return FALSE;

  op0 = XEXP (op, 0);
  if (GET_CODE (op0) == SUBREG)
    op0 = SUBREG_REG (op0);

  switch (GET_CODE (op))
    {
    default:
      break;

    case ABS:
    case NOT:
      if (GET_MODE (op) == SImode && GET_CODE (op0) == REG && GPR_P (REGNO (op0)))
	return TRUE;

      break;
    }

  return FALSE;
}

/* Return true if the add or subtraction can be executed with conditional
   execution.  */

int
condexec_addsub_operator (op, mode)
     rtx op;
     enum machine_mode mode ATTRIBUTE_UNUSED;
{
  rtx op0, op1;

  /* Only do this after register allocation, so that we can look at the register # */
  if (!reload_completed)
    return FALSE;

  if (GET_RTX_CLASS (GET_CODE (op)) != '2' && GET_RTX_CLASS (GET_CODE (op)) != 'c')
    return FALSE;

  op0 = XEXP (op, 0);
  op1 = XEXP (op, 1);

  if (GET_CODE (op0) == SUBREG)
    op0 = SUBREG_REG (op0);

  if (GET_CODE (op1) == SUBREG)
    op1 = SUBREG_REG (op1);

  if (GET_CODE (op0) != REG)
    return FALSE;

  switch (GET_CODE (op))
    {
    default:
      break;

    case PLUS:
    case MINUS:
      return (GET_MODE (op) == SImode && GPR_P (REGNO (op0))
	      && gpr_or_constant_operand (op1, SImode));
    }

  return FALSE;
}

/* Return true if the binary operator can be executed with conditional
   execution.  We don't include add/sub here, since they have extra
   clobbers for the flags registers.  */

int
condexec_binary_operator (op, mode)
     rtx op;
     enum machine_mode mode ATTRIBUTE_UNUSED;
{
  rtx op0, op1;

  /* Only do this after register allocation, so that we can look at the register # */
  if (!reload_completed)
    return FALSE;

  if (GET_RTX_CLASS (GET_CODE (op)) != '2' && GET_RTX_CLASS (GET_CODE (op)) != 'c')
    return FALSE;

  op0 = XEXP (op, 0);
  op1 = XEXP (op, 1);

  if (GET_CODE (op0) == SUBREG)
    op0 = SUBREG_REG (op0);

  if (GET_CODE (op1) == SUBREG)
    op1 = SUBREG_REG (op1);

  if (GET_CODE (op0) != REG)
    return FALSE;

  /* MULT is not included here, because it is an IU only instruction.  */
  switch (GET_CODE (op))
    {
    default:
      break;

    case AND:
    case IOR:
    case XOR:
    case ASHIFTRT:
    case LSHIFTRT:
    case ROTATERT:
      return (GET_MODE (op) == SImode && GPR_P (REGNO (op0))
	      && gpr_or_constant_operand (op1, SImode));

    case ASHIFT:
    case ROTATE:
      return (GET_MODE (op) == SImode && GPR_P (REGNO (op0))
	      && GET_CODE (op1) == CONST_INT);
    }

  return FALSE;
}

/* Return true if the shift/rotate left operator can be executed with
   conditional execution.  */

int
condexec_shiftl_operator (op, mode)
     rtx op;
     enum machine_mode mode ATTRIBUTE_UNUSED;
{
  rtx op0, op1;

  /* Only do this after register allocation, so that we can look at the register # */
  if (!reload_completed)
    return FALSE;

  if (GET_RTX_CLASS (GET_CODE (op)) != '2' && GET_RTX_CLASS (GET_CODE (op)) != 'c')
    return FALSE;

  op0 = XEXP (op, 0);
  op1 = XEXP (op, 1);

  if (GET_CODE (op0) == SUBREG)
    op0 = SUBREG_REG (op0);

  if (GET_CODE (op1) == SUBREG)
    op1 = SUBREG_REG (op1);

  if (GET_CODE (op0) != REG)
    return FALSE;

  switch (GET_CODE (op))
    {
    default:
      break;

    case ASHIFT:
    case ROTATE:
      return (GET_MODE (op) == SImode && GPR_P (REGNO (op0))
	      && GET_CODE (op1) == NEG
	      && GET_CODE (XEXP (op1, 0)) == REG
	      && GPR_P (REGNO (XEXP (op1, 0))));
    }

  return FALSE;
}

/* Return true if the {sign,zero} extend operator from memory can be
   conditionally executed.  */

int
condexec_extend_operator (op, mode)
     rtx op;
     enum machine_mode mode ATTRIBUTE_UNUSED;
{
  /* Only do this after register allocation, so that we can look at the register # */
  if (!reload_completed)
    return FALSE;

  if (GET_RTX_CLASS (GET_CODE (op)) != '1')
    return FALSE;

  switch (GET_CODE (op))
    {
    default:
      break;

    case SIGN_EXTEND:
    case ZERO_EXTEND:
      if ((GET_MODE (op) == SImode && GET_MODE (XEXP (op, 0)) == QImode)
	  || (GET_MODE (op) == SImode && GET_MODE (XEXP (op, 0)) == HImode)
	  || (GET_MODE (op) == HImode && GET_MODE (XEXP (op, 0)) == QImode))
	return TRUE;

      break;
    }

  return FALSE;
}

/* Return true for comparisons against 0 that can be turned into a
   bratnz/bratzr instruction.  */

int
branch_zero_operator (op, mode)
     rtx op;
     enum machine_mode mode;
{
  rtx x0, x1;

  if (GET_MODE (op) != mode && mode != VOIDmode)
    return FALSE;

  if (GET_CODE (op) != EQ && GET_CODE (op) != NE)
    return FALSE;

  x0 = XEXP (op, 0);
  if (GET_CODE (x0) != REG || !GPR_OR_PSEUDO_P (REGNO (x0)))
    return FALSE;

  x1 = XEXP (op, 1);
  if (GET_CODE (x1) != CONST_INT || INTVAL (x1) != 0)
    return FALSE;

  return TRUE;
}

/* Return true if an operand is simple, suitable for use as the destination of
   a conditional move */

int
cond_move_dest_operand (op, mode)
     register rtx op;
     enum machine_mode mode ATTRIBUTE_UNUSED;
{
  rtx addr;

  if (mode != QImode && mode != HImode && mode != SImode && mode != SFmode)
    return FALSE;

  switch (GET_CODE (op))
    {
    default:
      break;

    case REG:
    case SUBREG:
      return gpr_operand (op, mode);

    /* Don't allow post dec/inc, since we might not get the side effects correct. */
    case MEM:
      addr = XEXP (op, 0);
      return (GET_CODE (addr) != POST_DEC
	      && GET_CODE (addr) != POST_INC
	      && d30v_legitimate_address_p (mode, addr, reload_completed));
    }

  return FALSE;
}

/* Return true if an operand is simple, suitable for use in a conditional move */

int
cond_move_operand (op, mode)
     register rtx op;
     enum machine_mode mode ATTRIBUTE_UNUSED;
{
  rtx addr;

  if (mode != QImode && mode != HImode && mode != SImode && mode != SFmode)
    return FALSE;

  switch (GET_CODE (op))
    {
    default:
      break;

    case REG:
    case SUBREG:
      return gpr_operand (op, mode);

    case CONST_DOUBLE:
      return GET_MODE (op) == SFmode;

    case CONST_INT:
    case SYMBOL_REF:
    case LABEL_REF:
    case CONST:
      return TRUE;

    /* Don't allow post dec/inc, since we might not get the side effects correct. */
    case MEM:
      addr = XEXP (op, 0);
      return (GET_CODE (addr) != POST_DEC
	      && GET_CODE (addr) != POST_INC
	      && d30v_legitimate_address_p (mode, addr, reload_completed));
    }

  return FALSE;
}

/* Return true if an operand is simple, suitable for use in conditional execution.
   Unlike cond_move, we can allow auto inc/dec.  */

int
cond_exec_operand (op, mode)
     register rtx op;
     enum machine_mode mode;
{
  if (mode != QImode && mode != HImode && mode != SImode && mode != SFmode)
    return FALSE;

  switch (GET_CODE (op))
    {
    default:
      break;

    case REG:
    case SUBREG:
      return gpr_operand (op, mode);

    case CONST_DOUBLE:
      return GET_MODE (op) == SFmode;

    case CONST_INT:
    case SYMBOL_REF:
    case LABEL_REF:
    case CONST:
      return TRUE;

    case MEM:
      return memory_operand (op, mode);
    }

  return FALSE;
}

/* Return true if operand is a SI mode signed relational test.  */

int
srelational_si_operator (op, mode)
     register rtx op;
     enum machine_mode mode;
{
  rtx x0, x1;

  if (GET_MODE (op) != mode && mode != VOIDmode)
    return FALSE;

  switch (GET_CODE (op))
    {
    default:
      return FALSE;

    case EQ:
    case NE:
    case LT:
    case LE:
    case GT:
    case GE: