📄 frv.h
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/* Scratch registers used in the prologue, epilogue and thunks. OFFSET_REGNO is for loading constant addends that are too big for a single instruction. TEMP_REGNO is used for transferring SPRs to and from the stack, and various other activities. */#define OFFSET_REGNO 4#define TEMP_REGNO 5/* Registers used in the prologue. OLD_SP_REGNO is the old stack pointer, which is sometimes used to set up the frame pointer. */#define OLD_SP_REGNO 6/* Registers used in the epilogue. STACKADJ_REGNO stores the exception handler's stack adjustment. */#define STACKADJ_REGNO 6/* Registers used in thunks. JMP_REGNO is used for loading the target address. */#define JUMP_REGNO 6#define EH_RETURN_DATA_REGNO(N) ((N) <= (LAST_EH_REGNUM - FIRST_EH_REGNUM)? \ (N) + FIRST_EH_REGNUM : INVALID_REGNUM)#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, STACKADJ_REGNO)#define EH_RETURN_HANDLER_RTX RETURN_ADDR_RTX (0, frame_pointer_rtx)/* An initializer that says which registers are used for fixed purposes all throughout the compiled code and are therefore not available for general allocation. These would include the stack pointer, the frame pointer (except on machines where that can be used as a general register when no frame pointer is needed), the program counter on machines where that is considered one of the addressable registers, and any other numbered register with a standard use. This information is expressed as a sequence of numbers, separated by commas and surrounded by braces. The Nth number is 1 if register N is fixed, 0 otherwise. The table initialized from this macro, and the table initialized by the following one, may be overridden at run time either automatically, by the actions of the macro `CONDITIONAL_REGISTER_USAGE', or by the user with the command options `-ffixed-REG', `-fcall-used-REG' and `-fcall-saved-REG'. *//* gr0 -- Hard Zero gr1 -- Stack Pointer gr2 -- Frame Pointer gr3 -- Hidden Parameter gr16 -- Small Data reserved gr17 -- Pic reserved gr28 -- OS reserved gr29 -- OS reserved gr30 -- OS reserved gr31 -- OS reserved cr3 -- reserved to reload FCC registers. cr7 -- reserved to reload ICC registers. */#define FIXED_REGISTERS \{ /* Integer Registers */ \ 1, 1, 1, 1, 0, 0, 0, 0, /* 000-007, gr0 - gr7 */ \ 0, 0, 0, 0, 0, 0, 0, 0, /* 008-015, gr8 - gr15 */ \ 1, 1, 0, 0, 0, 0, 0, 0, /* 016-023, gr16 - gr23 */ \ 0, 0, 0, 0, 1, 1, 1, 1, /* 024-031, gr24 - gr31 */ \ 0, 0, 0, 0, 0, 0, 0, 0, /* 032-039, gr32 - gr39 */ \ 0, 0, 0, 0, 0, 0, 0, 0, /* 040-040, gr48 - gr47 */ \ 0, 0, 0, 0, 0, 0, 0, 0, /* 048-055, gr48 - gr55 */ \ 0, 0, 0, 0, 0, 0, 0, 0, /* 056-063, gr56 - gr63 */ \ /* Float Registers */ \ 0, 0, 0, 0, 0, 0, 0, 0, /* 064-071, fr0 - fr7 */ \ 0, 0, 0, 0, 0, 0, 0, 0, /* 072-079, fr8 - fr15 */ \ 0, 0, 0, 0, 0, 0, 0, 0, /* 080-087, fr16 - fr23 */ \ 0, 0, 0, 0, 0, 0, 0, 0, /* 088-095, fr24 - fr31 */ \ 0, 0, 0, 0, 0, 0, 0, 0, /* 096-103, fr32 - fr39 */ \ 0, 0, 0, 0, 0, 0, 0, 0, /* 104-111, fr48 - fr47 */ \ 0, 0, 0, 0, 0, 0, 0, 0, /* 112-119, fr48 - fr55 */ \ 0, 0, 0, 0, 0, 0, 0, 0, /* 120-127, fr56 - fr63 */ \ /* Condition Code Registers */ \ 0, 0, 0, 0, /* 128-131, fcc0 - fcc3 */ \ 0, 0, 0, 1, /* 132-135, icc0 - icc3 */ \ /* Conditional execution Registers (CCR) */ \ 0, 0, 0, 0, 0, 0, 0, 1, /* 136-143, cr0 - cr7 */ \ /* Accumulators */ \ 1, 1, 1, 1, 1, 1, 1, 1, /* 144-151, acc0 - acc7 */ \ 1, 1, 1, 1, 1, 1, 1, 1, /* 152-159, accg0 - accg7 */ \ /* Other registers */ \ 1, /* 160, AP - fake arg ptr */ \ 0, /* 161, LR - Link register*/ \ 0, /* 162, LCR - Loop count reg*/ \}/* Like `FIXED_REGISTERS' but has 1 for each register that is clobbered (in general) by function calls as well as for fixed registers. This macro therefore identifies the registers that are not available for general allocation of values that must live across function calls. If a register has 0 in `CALL_USED_REGISTERS', the compiler automatically saves it on function entry and restores it on function exit, if the register is used within the function. */#define CALL_USED_REGISTERS \{ /* Integer Registers */ \ 1, 1, 1, 1, 1, 1, 1, 1, /* 000-007, gr0 - gr7 */ \ 1, 1, 1, 1, 1, 1, 1, 1, /* 008-015, gr8 - gr15 */ \ 1, 1, 0, 0, 0, 0, 0, 0, /* 016-023, gr16 - gr23 */ \ 0, 0, 0, 0, 1, 1, 1, 1, /* 024-031, gr24 - gr31 */ \ 1, 1, 1, 1, 1, 1, 1, 1, /* 032-039, gr32 - gr39 */ \ 1, 1, 1, 1, 1, 1, 1, 1, /* 040-040, gr48 - gr47 */ \ 0, 0, 0, 0, 0, 0, 0, 0, /* 048-055, gr48 - gr55 */ \ 0, 0, 0, 0, 0, 0, 0, 0, /* 056-063, gr56 - gr63 */ \ /* Float Registers */ \ 1, 1, 1, 1, 1, 1, 1, 1, /* 064-071, fr0 - fr7 */ \ 1, 1, 1, 1, 1, 1, 1, 1, /* 072-079, fr8 - fr15 */ \ 0, 0, 0, 0, 0, 0, 0, 0, /* 080-087, fr16 - fr23 */ \ 0, 0, 0, 0, 0, 0, 0, 0, /* 088-095, fr24 - fr31 */ \ 1, 1, 1, 1, 1, 1, 1, 1, /* 096-103, fr32 - fr39 */ \ 1, 1, 1, 1, 1, 1, 1, 1, /* 104-111, fr48 - fr47 */ \ 0, 0, 0, 0, 0, 0, 0, 0, /* 112-119, fr48 - fr55 */ \ 0, 0, 0, 0, 0, 0, 0, 0, /* 120-127, fr56 - fr63 */ \ /* Condition Code Registers */ \ 1, 1, 1, 1, /* 128-131, fcc0 - fcc3 */ \ 1, 1, 1, 1, /* 132-135, icc0 - icc3 */ \ /* Conditional execution Registers (CCR) */ \ 1, 1, 1, 1, 1, 1, 1, 1, /* 136-143, cr0 - cr7 */ \ /* Accumulators */ \ 1, 1, 1, 1, 1, 1, 1, 1, /* 144-151, acc0 - acc7 */ \ 1, 1, 1, 1, 1, 1, 1, 1, /* 152-159, accg0 - accg7 */ \ /* Other registers */ \ 1, /* 160, AP - fake arg ptr */ \ 1, /* 161, LR - Link register*/ \ 1, /* 162, LCR - Loop count reg */ \}/* Zero or more C statements that may conditionally modify two variables `fixed_regs' and `call_used_regs' (both of type `char []') after they have been initialized from the two preceding macros. This is necessary in case the fixed or call-clobbered registers depend on target flags. You need not define this macro if it has no work to do. If the usage of an entire class of registers depends on the target flags, you may indicate this to GCC by using this macro to modify `fixed_regs' and `call_used_regs' to 1 for each of the registers in the classes which should not be used by GCC. Also define the macro `REG_CLASS_FROM_LETTER' to return `NO_REGS' if it is called with a letter for a class that shouldn't be used. (However, if this class is not included in `GENERAL_REGS' and all of the insn patterns whose constraints permit this class are controlled by target switches, then GCC will automatically avoid using these registers when the target switches are opposed to them.) */#define CONDITIONAL_REGISTER_USAGE frv_conditional_register_usage () /* Order of allocation of registers. *//* If defined, an initializer for a vector of integers, containing the numbers of hard registers in the order in which GNU CC should prefer to use them (from most preferred to least). If this macro is not defined, registers are used lowest numbered first (all else being equal). One use of this macro is on machines where the highest numbered registers must always be saved and the save-multiple-registers instruction supports only sequences of consecutive registers. On such machines, define `REG_ALLOC_ORDER' to be an initializer that lists the highest numbered allocatable register first. *//* On the FRV, allocate GR16 and GR17 after other saved registers so that we have a better chance of allocating 2 registers at a time and can use the double word load/store instructions in the prologue. */#define REG_ALLOC_ORDER \{ \ /* volatile registers */ \ GPR_FIRST + 4, GPR_FIRST + 5, GPR_FIRST + 6, GPR_FIRST + 7, \ GPR_FIRST + 8, GPR_FIRST + 9, GPR_FIRST + 10, GPR_FIRST + 11, \ GPR_FIRST + 12, GPR_FIRST + 13, GPR_FIRST + 14, GPR_FIRST + 15, \ GPR_FIRST + 32, GPR_FIRST + 33, GPR_FIRST + 34, GPR_FIRST + 35, \ GPR_FIRST + 36, GPR_FIRST + 37, GPR_FIRST + 38, GPR_FIRST + 39, \ GPR_FIRST + 40, GPR_FIRST + 41, GPR_FIRST + 42, GPR_FIRST + 43, \ GPR_FIRST + 44, GPR_FIRST + 45, GPR_FIRST + 46, GPR_FIRST + 47, \ \ FPR_FIRST + 0, FPR_FIRST + 1, FPR_FIRST + 2, FPR_FIRST + 3, \ FPR_FIRST + 4, FPR_FIRST + 5, FPR_FIRST + 6, FPR_FIRST + 7, \ FPR_FIRST + 8, FPR_FIRST + 9, FPR_FIRST + 10, FPR_FIRST + 11, \ FPR_FIRST + 12, FPR_FIRST + 13, FPR_FIRST + 14, FPR_FIRST + 15, \ FPR_FIRST + 32, FPR_FIRST + 33, FPR_FIRST + 34, FPR_FIRST + 35, \ FPR_FIRST + 36, FPR_FIRST + 37, FPR_FIRST + 38, FPR_FIRST + 39, \ FPR_FIRST + 40, FPR_FIRST + 41, FPR_FIRST + 42, FPR_FIRST + 43, \ FPR_FIRST + 44, FPR_FIRST + 45, FPR_FIRST + 46, FPR_FIRST + 47, \ \ ICC_FIRST + 0, ICC_FIRST + 1, ICC_FIRST + 2, ICC_FIRST + 3, \ FCC_FIRST + 0, FCC_FIRST + 1, FCC_FIRST + 2, FCC_FIRST + 3, \ CR_FIRST + 0, CR_FIRST + 1, CR_FIRST + 2, CR_FIRST + 3, \ CR_FIRST + 4, CR_FIRST + 5, CR_FIRST + 6, CR_FIRST + 7, \ \ /* saved registers */ \ GPR_FIRST + 18, GPR_FIRST + 19, \ GPR_FIRST + 20, GPR_FIRST + 21, GPR_FIRST + 22, GPR_FIRST + 23, \ GPR_FIRST + 24, GPR_FIRST + 25, GPR_FIRST + 26, GPR_FIRST + 27, \ GPR_FIRST + 48, GPR_FIRST + 49, GPR_FIRST + 50, GPR_FIRST + 51, \ GPR_FIRST + 52, GPR_FIRST + 53, GPR_FIRST + 54, GPR_FIRST + 55, \ GPR_FIRST + 56, GPR_FIRST + 57, GPR_FIRST + 58, GPR_FIRST + 59, \ GPR_FIRST + 60, GPR_FIRST + 61, GPR_FIRST + 62, GPR_FIRST + 63, \ GPR_FIRST + 16, GPR_FIRST + 17, \ \ FPR_FIRST + 16, FPR_FIRST + 17, FPR_FIRST + 18, FPR_FIRST + 19, \ FPR_FIRST + 20, FPR_FIRST + 21, FPR_FIRST + 22, FPR_FIRST + 23, \ FPR_FIRST + 24, FPR_FIRST + 25, FPR_FIRST + 26, FPR_FIRST + 27, \ FPR_FIRST + 28, FPR_FIRST + 29, FPR_FIRST + 30, FPR_FIRST + 31, \ FPR_FIRST + 48, FPR_FIRST + 49, FPR_FIRST + 50, FPR_FIRST + 51, \ FPR_FIRST + 52, FPR_FIRST + 53, FPR_FIRST + 54, FPR_FIRST + 55, \ FPR_FIRST + 56, FPR_FIRST + 57, FPR_FIRST + 58, FPR_FIRST + 59, \ FPR_FIRST + 60, FPR_FIRST + 61, FPR_FIRST + 62, FPR_FIRST + 63, \ \ /* special or fixed registers */ \ GPR_FIRST + 0, GPR_FIRST + 1, GPR_FIRST + 2, GPR_FIRST + 3, \ GPR_FIRST + 28, GPR_FIRST + 29, GPR_FIRST + 30, GPR_FIRST + 31, \ ACC_FIRST + 0, ACC_FIRST + 1, ACC_FIRST + 2, ACC_FIRST + 3, \ ACC_FIRST + 4, ACC_FIRST + 5, ACC_FIRST + 6, ACC_FIRST + 7, \ ACCG_FIRST + 0, ACCG_FIRST + 1, ACCG_FIRST + 2, ACCG_FIRST + 3, \ ACCG_FIRST + 4, ACCG_FIRST + 5, ACCG_FIRST + 6, ACCG_FIRST + 7, \ AP_FIRST, LR_REGNO, LCR_REGNO \} /* How Values Fit in Registers. *//* A C expression for the number of consecutive hard registers, starting at register number REGNO, required to hold a value of mode MODE. On a machine where all registers are exactly one word, a suitable definition of this macro is #define HARD_REGNO_NREGS(REGNO, MODE) \ ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) \ / UNITS_PER_WORD)) *//* On the FRV, make the CC modes take 3 words in the integer registers, so that we can build the appropriate instructions to properly reload the values. */#define HARD_REGNO_NREGS(REGNO, MODE) frv_hard_regno_nregs (REGNO, MODE)/* A C expression that is nonzero if it is permissible to store a value of mode MODE in hard register number REGNO (or in several registers starting with that one). For a machine where all registers are equivalent, a suitable definition is #define HARD_REGNO_MODE_OK(REGNO, MODE) 1 It is not necessary for this macro to check for the numbers of fixed registers, because the allocation mechanism considers them to be always occupied. On some machines, double-precision values must be kept in even/odd register pairs. The way to implement that is to define this macro to reject odd register numbers for such modes. The minimum requirement for a mode to be OK in a register is that the `movMODE' instruction pattern support moves between the register and any other hard register for which the mode is OK; and that moving a value into the register and back out not alter it. Since the same instruction used to move `SImode' will work for all narrower integer modes, it is not necessary on any machine for `HARD_REGNO_MODE_OK' to distinguish between these modes, provided you define patterns `movhi', etc., to take advantage of this. This is useful because of the interaction between `HARD_REGNO_MODE_OK' and `MODES_TIEABLE_P'; it is very desirable for all integer modes to be tieable. Many machines have special registers for floating point arithmetic. Often people assume that floating point machine modes are allowed only in floating point registers. This is not true. Any registers that can hold integers can safely *hold* a floating point machine mode, whether or not floating arithmetic can be done on it in those registers. Integer move instructions can be used to move the values. On some machines, though, the converse is true: fixed-point machine modes may not go in floating registers. This is true if the floating registers normalize any value stored in them, because storing a non-floating value there would garble it. In this case, `HARD_REGNO_MODE_OK' should reject fixed-point machine modes in floating registers. But if the floating registers do not automatically normalize, if you can store any bit pattern in one and retrieve it unchanged without a trap, then any machine mode may go in a floating register, so you can define this macro to say so. The primary significance of special floating registers is rather that they are the registers acceptable in floating point arithmetic instructions. However, this is of no concern to `HARD_REGNO_MODE_OK'. You handle it by writing the proper constraints for those instructions. On some machines, the floating registers are especially slow to access, so that it is better to store a value in a stack frame than in such a register if floating point arithmetic is not being done. As long as the floating registers are not in class `GENERAL_REGS', they will not be used unless some pattern's constraint asks for one. */#define HARD_REGNO_MODE_OK(REGNO, MODE) frv_hard_regno_mode_ok (REGNO, MODE)/* A C expression that is nonzero if it is desirable to choose register allocation so as to avoid move instructions between a value of mode MODE1 and a value of mode MODE2.⌨️ 快捷键说明
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