frv.c

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   sense on a particular target machine.  You can define a macro
   `OVERRIDE_OPTIONS' to take account of this.  This macro, if
   defined, is executed once just after all the command options have
   been parsed.

   Don't use this macro to turn on various extra optimizations for
   `-O'.  That is what `OPTIMIZATION_OPTIONS' is for.  */

void
frv_override_options ()
{
  int regno, i;

  /* Set the cpu type */
  if (frv_cpu_string)
    {
      if (strcmp (frv_cpu_string, "simple") == 0)
	frv_cpu_type = FRV_CPU_SIMPLE;

      else if (strcmp (frv_cpu_string, "tomcat") == 0)
	frv_cpu_type = FRV_CPU_TOMCAT;

      else if (strncmp (frv_cpu_string, "fr", sizeof ("fr")-1) != 0)
	error ("Unknown cpu: -mcpu=%s", frv_cpu_string);

      else
	{
	  const char *p = frv_cpu_string + sizeof ("fr") - 1;
	  if (strcmp (p, "500") == 0)
	    frv_cpu_type = FRV_CPU_FR500;

	  else if (strcmp (p, "400") == 0)
	    frv_cpu_type = FRV_CPU_FR400;

	  else if (strcmp (p, "300") == 0)
	    frv_cpu_type = FRV_CPU_FR300;

	  else if (strcmp (p, "v") == 0)
	    frv_cpu_type = FRV_CPU_GENERIC;

	  else
	    error ("Unknown cpu: -mcpu=%s", frv_cpu_string);
	}
    }

  target_flags |= (frv_default_flags_for_cpu () & ~target_flags_explicit);

  /* -mlibrary-pic sets -fPIC and -G0 and also suppresses warnings from the
     linker about linking pic and non-pic code.  */
  if (TARGET_LIBPIC)
    {
      if (!flag_pic)		/* -fPIC */
	flag_pic = 2;

      if (! g_switch_set)	/* -G0 */
	{
	  g_switch_set = 1;
	  g_switch_value = 0;
	}
    }

  /* Both -fpic and -gdwarf want to use .previous and the assembler only keeps
     one level.  */
  if (write_symbols == DWARF_DEBUG && flag_pic)
    error ("-fpic and -gdwarf are incompatible (-fpic and -g/-gdwarf-2 are fine)");

  /* Change the branch cost value */
  if (frv_branch_cost_string)
    frv_branch_cost_int = atoi (frv_branch_cost_string);

  /* Change the # of insns to be converted to conditional execution */
  if (frv_condexec_insns_str)
    frv_condexec_insns = atoi (frv_condexec_insns_str);

  /* Change # of temporary registers used to hold integer constants */
  if (frv_condexec_temps_str)
    frv_condexec_temps = atoi (frv_condexec_temps_str);

  /* Change scheduling look ahead. */
  if (frv_sched_lookahead_str)
    frv_sched_lookahead = atoi (frv_sched_lookahead_str);

  /* A C expression whose value is a register class containing hard
     register REGNO.  In general there is more than one such class;
     choose a class which is "minimal", meaning that no smaller class
     also contains the register. */

  for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
    {
      enum reg_class class;

      if (GPR_P (regno))
	{
	  int gpr_reg = regno - GPR_FIRST;
	  if ((gpr_reg & 3) == 0)
	    class = QUAD_REGS;

	  else if ((gpr_reg & 1) == 0)
	    class = EVEN_REGS;

	  else
	    class = GPR_REGS;
	}

      else if (FPR_P (regno))
	{
	  int fpr_reg = regno - GPR_FIRST;
	  if ((fpr_reg & 3) == 0)
	    class = QUAD_FPR_REGS;

	  else if ((fpr_reg & 1) == 0)
	    class = FEVEN_REGS;

	  else
	    class = FPR_REGS;
	}

      else if (regno == LR_REGNO)
	class = LR_REG;

      else if (regno == LCR_REGNO)
	class = LCR_REG;

      else if (ICC_P (regno))
	class = ICC_REGS;

      else if (FCC_P (regno))
	class = FCC_REGS;

      else if (ICR_P (regno))
	class = ICR_REGS;

      else if (FCR_P (regno))
	class = FCR_REGS;

      else if (ACC_P (regno))
	{
	  int r = regno - ACC_FIRST;
	  if ((r & 3) == 0)
	    class = QUAD_ACC_REGS;
	  else if ((r & 1) == 0)
	    class = EVEN_ACC_REGS;
	  else
	    class = ACC_REGS;
	}

      else if (ACCG_P (regno))
	class = ACCG_REGS;

      else
	class = NO_REGS;

      regno_reg_class[regno] = class;
    }

  /* Check for small data option */
  if (!g_switch_set)
    g_switch_value = SDATA_DEFAULT_SIZE;

  /* A C expression which defines the machine-dependent operand
     constraint letters for register classes.  If CHAR is such a
     letter, the value should be the register class corresponding to
     it.  Otherwise, the value should be `NO_REGS'.  The register
     letter `r', corresponding to class `GENERAL_REGS', will not be
     passed to this macro; you do not need to handle it.

     The following letters are unavailable, due to being used as
     constraints:
	'0'..'9'
	'<', '>'
	'E', 'F', 'G', 'H'
	'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P'
	'Q', 'R', 'S', 'T', 'U'
	'V', 'X'
	'g', 'i', 'm', 'n', 'o', 'p', 'r', 's' */

  for (i = 0; i < 256; i++)
    reg_class_from_letter[i] = NO_REGS;

  reg_class_from_letter['a'] = ACC_REGS;
  reg_class_from_letter['b'] = EVEN_ACC_REGS;
  reg_class_from_letter['c'] = CC_REGS;
  reg_class_from_letter['d'] = GPR_REGS;
  reg_class_from_letter['e'] = EVEN_REGS;
  reg_class_from_letter['f'] = FPR_REGS;
  reg_class_from_letter['h'] = FEVEN_REGS;
  reg_class_from_letter['l'] = LR_REG;
  reg_class_from_letter['q'] = QUAD_REGS;
  reg_class_from_letter['t'] = ICC_REGS;
  reg_class_from_letter['u'] = FCC_REGS;
  reg_class_from_letter['v'] = ICR_REGS;
  reg_class_from_letter['w'] = FCR_REGS;
  reg_class_from_letter['x'] = QUAD_FPR_REGS;
  reg_class_from_letter['y'] = LCR_REG;
  reg_class_from_letter['z'] = SPR_REGS;
  reg_class_from_letter['A'] = QUAD_ACC_REGS;
  reg_class_from_letter['B'] = ACCG_REGS;
  reg_class_from_letter['C'] = CR_REGS;

  /* There is no single unaligned SI op for PIC code.  Sometimes we
     need to use ".4byte" and sometimes we need to use ".picptr".
     See frv_assemble_integer for details.  */
  if (flag_pic)
    targetm.asm_out.unaligned_op.si = 0;

  init_machine_status = frv_init_machine_status;
}


/* Some machines may desire to change what optimizations are performed for
   various optimization levels.  This macro, if defined, is executed once just
   after the optimization level is determined and before the remainder of the
   command options have been parsed.  Values set in this macro are used as the
   default values for the other command line options.

   LEVEL is the optimization level specified; 2 if `-O2' is specified, 1 if
   `-O' is specified, and 0 if neither is specified.

   SIZE is nonzero if `-Os' is specified, 0 otherwise.

   You should not use this macro to change options that are not
   machine-specific.  These should uniformly selected by the same optimization
   level on all supported machines.  Use this macro to enable machbine-specific
   optimizations.

   *Do not examine `write_symbols' in this macro!* The debugging options are
   *not supposed to alter the generated code.  */

/* On the FRV, possibly disable VLIW packing which is done by the 2nd
   scheduling pass at the current time.  */
void
frv_optimization_options (level, size)
     int level;
     int size ATTRIBUTE_UNUSED;
{
  if (level >= 2)
    {
#ifdef DISABLE_SCHED2
      flag_schedule_insns_after_reload = 0;
#endif
#ifdef ENABLE_RCSP
      flag_rcsp = 1;
#endif
    }
}


/* Return true if NAME (a STRING_CST node) begins with PREFIX.  */

static int
frv_string_begins_with (name, prefix)
     tree name;
     const char *prefix;
{
  int prefix_len = strlen (prefix);

  /* Remember: NAME's length includes the null terminator.  */
  return (TREE_STRING_LENGTH (name) > prefix_len
	  && strncmp (TREE_STRING_POINTER (name), prefix, prefix_len) == 0);
}

/* Encode section information of DECL, which is either a VAR_DECL,
   FUNCTION_DECL, STRING_CST, CONSTRUCTOR, or ???.

   For the FRV we want to record:

   - whether the object lives in .sdata/.sbss.
     objects living in .sdata/.sbss are prefixed with SDATA_FLAG_CHAR

*/

static void
frv_encode_section_info (decl, first)
     tree decl;
     int first;
{
  if (! first)
    return;
  if (TREE_CODE (decl) == VAR_DECL)
    {
      int size = int_size_in_bytes (TREE_TYPE (decl));
      tree section_name = DECL_SECTION_NAME (decl);
      int is_small = 0;

      /* Don't apply the -G flag to internal compiler structures.  We
	 should leave such structures in the main data section, partly
	 for efficiency and partly because the size of some of them
	 (such as C++ typeinfos) is not known until later.  */
      if (!DECL_ARTIFICIAL (decl) && size > 0 && size <= g_switch_value)
	is_small = 1;

      /* If we already know which section the decl should be in, see if
	 it's a small data section.  */
      if (section_name)
	{
	  if (TREE_CODE (section_name) == STRING_CST)
	    {
	      if (frv_string_begins_with (section_name, ".sdata"))
		is_small = 1;
	      if (frv_string_begins_with (section_name, ".sbss"))
		is_small = 1;
	    }
	  else
	    abort ();
	}

      if (is_small)
	{
	  rtx sym_ref = XEXP (DECL_RTL (decl), 0);
	  char * str = xmalloc (2 + strlen (XSTR (sym_ref, 0)));

	  str[0] = SDATA_FLAG_CHAR;
	  strcpy (&str[1], XSTR (sym_ref, 0));
	  XSTR (sym_ref, 0) = str;
	}
    }
}


/* Zero or more C statements that may conditionally modify two variables
   `fixed_regs' and `call_used_regs' (both of type `char []') after they have
   been initialized from the two preceding macros.

   This is necessary in case the fixed or call-clobbered registers depend on
   target flags.

   You need not define this macro if it has no work to do.

   If the usage of an entire class of registers depends on the target flags,
   you may indicate this to GCC by using this macro to modify `fixed_regs' and
   `call_used_regs' to 1 for each of the registers in the classes which should
   not be used by GCC.  Also define the macro `REG_CLASS_FROM_LETTER' to return
   `NO_REGS' if it is called with a letter for a class that shouldn't be used.

   (However, if this class is not included in `GENERAL_REGS' and all of the
   insn patterns whose constraints permit this class are controlled by target
   switches, then GCC will automatically avoid using these registers when the
   target switches are opposed to them.)  */

void
frv_conditional_register_usage ()
{
  int i;

  for (i = GPR_FIRST + NUM_GPRS; i <= GPR_LAST; i++)
    fixed_regs[i] = call_used_regs[i] = 1;

  for (i = FPR_FIRST + NUM_FPRS; i <= FPR_LAST; i++)
    fixed_regs[i] = call_used_regs[i] = 1;

  for (i = ACC_FIRST + NUM_ACCS; i <= ACC_LAST; i++)
    fixed_regs[i] = call_used_regs[i] = 1;

  for (i = ACCG_FIRST + NUM_ACCS; i <= ACCG_LAST; i++)
    fixed_regs[i] = call_used_regs[i] = 1;

  /* Reserve the registers used for conditional execution.  At present, we need
     1 ICC and 1 ICR register.  */
  fixed_regs[ICC_TEMP] = call_used_regs[ICC_TEMP] = 1;
  fixed_regs[ICR_TEMP] = call_used_regs[ICR_TEMP] = 1;

  if (TARGET_FIXED_CC)
    {
      fixed_regs[ICC_FIRST] = call_used_regs[ICC_FIRST] = 1;
      fixed_regs[FCC_FIRST] = call_used_regs[FCC_FIRST] = 1;
      fixed_regs[ICR_FIRST] = call_used_regs[ICR_FIRST] = 1;
      fixed_regs[FCR_FIRST] = call_used_regs[FCR_FIRST] = 1;
    }

#if 0
  /* If -fpic, SDA_BASE_REG is the PIC register.  */
  if (g_switch_value == 0 && !flag_pic)
    fixed_regs[SDA_BASE_REG] = call_used_regs[SDA_BASE_REG] = 0;

  if (!flag_pic)
    fixed_regs[PIC_REGNO] = call_used_regs[PIC_REGNO] = 0;
#endif
}


/*
 * Compute the stack frame layout
 *
 * Register setup:
 * +---------------+-----------------------+-----------------------+
 * |Register       |type                   |caller-save/callee-save|