frv.md

linux下的gcc编译器

  ""
  "sethi #gprelhi(%1), %0"
  [(set_attr "type" "sethi")
   (set_attr "length" "4")])

(define_insn "movsi_lo_sum_pic"
  [(set (match_operand:SI 0 "integer_register_operand" "+d")
	(lo_sum:SI (match_dup 0)
		   (match_operand:SI 1 "pic_symbolic_operand" "")))]
  ""
  "setlo #gprello(%1), %0"
  [(set_attr "type" "setlo")
   (set_attr "length" "4")])

(define_expand "movdi"
  [(set (match_operand:DI 0 "nonimmediate_operand" "")
	(match_operand:DI 1 "general_operand" ""))]
  ""
  "
{
  if (!reload_in_progress
      && !reload_completed
      && !register_operand (operands[0], DImode)
      && !reg_or_0_operand (operands[1], DImode))
    operands[1] = copy_to_mode_reg (DImode, operands[1]);
}")

(define_insn "*movdi_double"
  [(set (match_operand:DI 0 "move_destination_operand" "=e,?h,??d,??f,R,?R,??m,??m,e,?h,??d,??f,?e,??d,?h,??f,R,m,e,??d,e,??d,?h,??f")
	(match_operand:DI 1 "move_source_operand"      " e,h,d,f,e,h,d,f,R,R,m,m,h,f,e,d,GO,GO,GO,GO,nF,nF,GO,GO"))]
  "TARGET_DOUBLE
   && (register_operand (operands[0], DImode)
       || reg_or_0_operand (operands[1], DImode))"
  "* return output_move_double (operands, insn);"
  [(set_attr "length" "8,4,8,8,4,4,8,8,4,4,8,8,4,8,4,8,4,8,8,8,16,16,8,8")
   (set_attr "type" "multi,fdconv,multi,multi,gstore,fstore,gstore,fstore,gload,fload,gload,fload,movfg,movfg,movgf,movgf,gstore,gstore,multi,multi,multi,multi,movgf,movgf")])

(define_insn "*movdi_nodouble"
  [(set (match_operand:DI 0 "move_destination_operand" "=e,?h,??d,??f,R,?R,??m,??m,e,?h,??d,??f,?e,??d,?h,??f,R,m,e,??d,e,??d,?h,??f")
	(match_operand:DI 1 "move_source_operand"      " e,h,d,f,e,h,d,f,R,R,m,m,h,f,e,d,GO,GO,GO,GO,nF,nF,GO,GO"))]
  "!TARGET_DOUBLE
   && (register_operand (operands[0], DImode)
       || reg_or_0_operand (operands[1], DImode))"
  "* return output_move_double (operands, insn);"
  [(set_attr "length" "8,8,8,8,4,4,8,8,4,4,8,8,8,8,8,8,4,8,8,8,16,16,8,8")
   (set_attr "type" "multi,multi,multi,multi,gstore,fstore,gstore,fstore,gload,fload,gload,fload,movfg,movfg,movgf,movgf,gstore,gstore,multi,multi,multi,multi,movgf,movgf")])

(define_split
  [(set (match_operand:DI 0 "register_operand" "")
	(match_operand:DI 1 "dbl_memory_two_insn_operand" ""))]
  "reload_completed"
  [(const_int 0)]
  "frv_split_double_load (operands[0], operands[1]);")

(define_split
  [(set (match_operand:DI 0 "odd_reg_operand" "")
	(match_operand:DI 1 "memory_operand" ""))]
  "reload_completed"
  [(const_int 0)]
  "frv_split_double_load (operands[0], operands[1]);")

(define_split
  [(set (match_operand:DI 0 "dbl_memory_two_insn_operand" "")
	(match_operand:DI 1 "reg_or_0_operand" ""))]
  "reload_completed"
  [(const_int 0)]
  "frv_split_double_store (operands[0], operands[1]);")

(define_split
  [(set (match_operand:DI 0 "memory_operand" "")
	(match_operand:DI 1 "odd_reg_operand" ""))]
  "reload_completed"
  [(const_int 0)]
  "frv_split_double_store (operands[0], operands[1]);")

(define_split
  [(set (match_operand:DI 0 "register_operand" "")
	(match_operand:DI 1 "register_operand" ""))]
  "reload_completed
   && (odd_reg_operand (operands[0], DImode)
       || odd_reg_operand (operands[1], DImode)
       || (integer_register_operand (operands[0], DImode)
	   && integer_register_operand (operands[1], DImode))
       || (!TARGET_DOUBLE
	   && fpr_operand (operands[0], DImode)
	   && fpr_operand (operands[1], DImode)))"
  [(set (match_dup 2) (match_dup 4))
   (set (match_dup 3) (match_dup 5))]
  "
{
  rtx op0      = operands[0];
  rtx op0_low  = gen_lowpart (SImode, op0);
  rtx op0_high = gen_highpart (SImode, op0);
  rtx op1      = operands[1];
  rtx op1_low  = gen_lowpart (SImode, op1);
  rtx op1_high = gen_highpart (SImode, op1);

  /* We normally copy the low-numbered register first.  However, if the first
     register operand 0 is the same as the second register of operand 1, we
     must copy in the opposite order.  */

  if (REGNO (op0_high) == REGNO (op1_low))
    {
      operands[2] = op0_low;
      operands[3] = op0_high;
      operands[4] = op1_low;
      operands[5] = op1_high;
    }
  else
    {
      operands[2] = op0_high;
      operands[3] = op0_low;
      operands[4] = op1_high;
      operands[5] = op1_low;
    }
}")

(define_split
  [(set (match_operand:DI 0 "register_operand" "")
	(match_operand:DI 1 "const_int_operand" ""))]
  "reload_completed"
  [(set (match_dup 2) (match_dup 4))
   (set (match_dup 3) (match_dup 1))]
  "
{
  rtx op0 = operands[0];
  rtx op1 = operands[1];

  operands[2] = gen_highpart (SImode, op0);
  operands[3] = gen_lowpart (SImode, op0);
  operands[4] = GEN_INT ((INTVAL (op1) < 0) ? -1 : 0);
}")

(define_split
  [(set (match_operand:DI 0 "register_operand" "")
	(match_operand:DI 1 "const_double_operand" ""))]
  "reload_completed"
  [(set (match_dup 2) (match_dup 4))
   (set (match_dup 3) (match_dup 5))]
  "
{
  rtx op0 = operands[0];
  rtx op1 = operands[1];

  operands[2] = gen_highpart (SImode, op0);
  operands[3] = gen_lowpart (SImode, op0);
  operands[4] = GEN_INT (CONST_DOUBLE_HIGH (op1));
  operands[5] = GEN_INT (CONST_DOUBLE_LOW (op1));
}")

;; Floating Point Moves
;;
;; Note - Patterns for SF mode moves are compulsory, but
;; patterns for DF are optional, as GCC can synthesize them.

(define_expand "movsf"
  [(set (match_operand:SF 0 "general_operand" "")
	(match_operand:SF 1 "general_operand" ""))]
  ""
  "
{
  if (!reload_in_progress
      && !reload_completed
      && !register_operand (operands[0], SFmode)
      && !reg_or_0_operand (operands[1], SFmode))
    operands[1] = copy_to_mode_reg (SFmode, operands[1]);
}")

(define_split
  [(set (match_operand:SF 0 "integer_register_operand" "")
	(match_operand:SF 1 "int_2word_operand" ""))]
  "reload_completed"
  [(set (match_dup 0)
	(high:SF (match_dup 1)))
   (set (match_dup 0)
	(lo_sum:SF (match_dup 0)
		(match_dup 1)))]
  "")

(define_insn "*movsf_load_has_fprs"
  [(set (match_operand:SF 0 "register_operand" "=f,d")
	(match_operand:SF 1 "frv_load_operand" "m,m"))]
  "TARGET_HAS_FPRS"
  "* return output_move_single (operands, insn);"
  [(set_attr "length" "4")
   (set_attr "type" "fload,gload")])

(define_insn "*movsf_internal_has_fprs"
  [(set (match_operand:SF 0 "move_destination_operand" "=f,f,m,m,?f,?d,?d,m,?d")
	(match_operand:SF 1 "move_source_operand" "f,OG,f,OG,d,f,d,d,F"))]
  "TARGET_HAS_FPRS
   && (register_operand (operands[0], SFmode) || reg_or_0_operand (operands[1], SFmode))"
  "* return output_move_single (operands, insn);"
  [(set_attr "length" "4,4,4,4,4,4,4,4,8")
   (set_attr "type" "fsconv,movgf,fstore,gstore,movgf,movfg,int,gstore,multi")])

;; If we don't support the double instructions, prefer gprs over fprs, since it
;; will all be emulated
(define_insn "*movsf_internal_no_fprs"
  [(set (match_operand:SF 0 "move_destination_operand" "=d,d,m,d,d")
	(match_operand:SF 1 "move_source_operand"      " d,OG,dOG,m,F"))]
  "!TARGET_HAS_FPRS
   && (register_operand (operands[0], SFmode) || reg_or_0_operand (operands[1], SFmode))"
  "* return output_move_single (operands, insn);"
  [(set_attr "length" "4,4,4,4,8")
   (set_attr "type" "int,int,gstore,gload,multi")])

(define_insn "movsf_high"
  [(set (match_operand:SF 0 "integer_register_operand" "=d")
	(high:SF (match_operand:SF 1 "int_2word_operand" "i")))]
  ""
  "sethi #hi(%1), %0"
  [(set_attr "type" "sethi")
   (set_attr "length" "4")])

(define_insn "movsf_lo_sum"
  [(set (match_operand:SF 0 "integer_register_operand" "+d")
	(lo_sum:SF (match_dup 0)
		   (match_operand:SF 1 "int_2word_operand" "i")))]
  ""
  "setlo #lo(%1), %0"
  [(set_attr "type" "setlo")
   (set_attr "length" "4")])

(define_expand "movdf"
  [(set (match_operand:DF 0 "nonimmediate_operand" "")
	(match_operand:DF 1 "general_operand" ""))]
  ""
  "
{
  if (!reload_in_progress
      && !reload_completed
      && !register_operand (operands[0], DFmode)
      && !reg_or_0_operand (operands[1], DFmode))
    operands[1] = copy_to_mode_reg (DFmode, operands[1]);
}")

(define_insn "*movdf_double"
  [(set (match_operand:DF 0 "move_destination_operand" "=h,?e,??f,??d,R,?R,??m,??m,h,?e,??f,??d,?h,??f,?e,??d,R,m,h,??f,e,??d")
	(match_operand:DF 1 "move_source_operand"      " h,e,f,d,h,e,f,d,R,R,m,m,e,d,h,f,GO,GO,GO,GO,GO,GO"))]
  "TARGET_DOUBLE
   && (register_operand (operands[0], DFmode)
       || reg_or_0_operand (operands[1], DFmode))"
  "* return output_move_double (operands, insn);"
  [(set_attr "length" "4,8,8,8,4,4,8,8,4,4,8,8,4,8,4,8,4,8,8,8,8,8")
   (set_attr "type" "fdconv,multi,multi,multi,fstore,gstore,fstore,gstore,fload,gload,fload,gload,movgf,movgf,movfg,movfg,gstore,gstore,movgf,movgf,multi,multi")])

;; If we don't support the double instructions, prefer gprs over fprs, since it
;; will all be emulated
(define_insn "*movdf_nodouble"
  [(set (match_operand:DF 0 "move_destination_operand" "=e,?h,??d,??f,R,?R,??m,??m,e,?h,??d,??f,?e,??d,?h,??f,R,m,e,??d,e,??d,?h,??f")
	(match_operand:DF 1 "move_source_operand"      " e,h,d,f,e,h,d,f,R,R,m,m,h,f,e,d,GO,GO,GO,GO,nF,nF,GO,GO"))]
  "!TARGET_DOUBLE
   && (register_operand (operands[0], DFmode)
       || reg_or_0_operand (operands[1], DFmode))"
  "* return output_move_double (operands, insn);"
  [(set_attr "length" "8,8,8,8,4,4,8,8,4,4,8,8,8,8,8,8,4,8,8,8,16,16,8,8")
   (set_attr "type" "multi,multi,multi,multi,gstore,fstore,gstore,fstore,gload,fload,gload,fload,movfg,movfg,movgf,movgf,gstore,gstore,multi,multi,multi,multi,movgf,movgf")])

(define_split
  [(set (match_operand:DF 0 "register_operand" "")
	(match_operand:DF 1 "dbl_memory_two_insn_operand" ""))]
  "reload_completed"
  [(const_int 0)]
  "frv_split_double_load (operands[0], operands[1]);")

(define_split
  [(set (match_operand:DF 0 "odd_reg_operand" "")
	(match_operand:DF 1 "memory_operand" ""))]
  "reload_completed"
  [(const_int 0)]
  "frv_split_double_load (operands[0], operands[1]);")

(define_split
  [(set (match_operand:DF 0 "dbl_memory_two_insn_operand" "")
	(match_operand:DF 1 "reg_or_0_operand" ""))]
  "reload_completed"
  [(const_int 0)]
  "frv_split_double_store (operands[0], operands[1]);")

(define_split
  [(set (match_operand:DF 0 "memory_operand" "")
	(match_operand:DF 1 "odd_reg_operand" ""))]
  "reload_completed"
  [(const_int 0)]
  "frv_split_double_store (operands[0], operands[1]);")

(define_split
  [(set (match_operand:DF 0 "register_operand" "")
	(match_operand:DF 1 "register_operand" ""))]
  "reload_completed
   && (odd_reg_operand (operands[0], DFmode)
       || odd_reg_operand (operands[1], DFmode)
       || (integer_register_operand (operands[0], DFmode)
	   && integer_register_operand (operands[1], DFmode))
       || (!TARGET_DOUBLE
	   && fpr_operand (operands[0], DFmode)
	   && fpr_operand (operands[1], DFmode)))"
  [(set (match_dup 2) (match_dup 4))
   (set (match_dup 3) (match_dup 5))]
  "
{
  rtx op0      = operands[0];
  rtx op0_low  = gen_lowpart (SImode, op0);
  rtx op0_high = gen_highpart (SImode, op0);
  rtx op1      = operands[1];
  rtx op1_low  = gen_lowpart (SImode, op1);
  rtx op1_high = gen_highpart (SImode, op1);

  /* We normally copy the low-numbered register first.  However, if the first
     register operand 0 is the same as the second register of operand 1, we
     must copy in the opposite order.  */

  if (REGNO (op0_high) == REGNO (op1_low))
    {
      operands[2] = op0_low;
      operands[3] = op0_high;
      operands[4] = op1_low;
      operands[5] = op1_high;
    }
  else
    {
      operands[2] = op0_high;
      operands[3] = op0_low;
      operands[4] = op1_high;
      operands[5] = op1_low;
    }
}")

(define_split
  [(set (match_operand:DF 0 "register_operand" "")
	(match_operand:DF 1 "const_int_operand" ""))]
  "reload_completed"
  [(set (match_dup 2) (match_dup 4))
   (set (match_dup 3) (match_dup 1))]
  "
{
  rtx op0 = operands[0];
  rtx op1 = operands[1];

  operands[2] = gen_highpart (SImode, op0);
  operands[3] = gen_lowpart (SImode, op0);
  operands[4] = GEN_INT ((INTVAL (op1) < 0) ? -1 : 0);
}")

(define_split
  [(set (match_operand:DF 0 "register_operand" "")
	(match_operand:DF 1 "const_double_operand" ""))]
  "reload_completed"
  [(set (match_dup 2) (match_dup 4))
   (set (match_dup 3) (match_dup 5))]
  "
{
  rtx op0 = operands[0];
  rtx op1 = operands[1];
  REAL_VALUE_TYPE rv;
  long l[2];

  REAL_VALUE_FROM_CONST_DOUBLE (rv, op1);
  REAL_VALUE_TO_TARGET_DOUBLE (rv, l);

  operands[2] = ge