frv.md

linux下的gcc编译器

(define_attr "type"
  "int,sethi,setlo,mul,div,gload,gstore,fload,fstore,movfg,movgf,branch,jump,jumpl,call,spr,trap,fsconv,fsadd,fsmul,fmas,fsdiv,sqrt_single,fdconv,fdadd,fdmul,fddiv,sqrt_double,mlogic,maveh,msath,maddh,mqaddh,mpackh,munpackh,mdpackh,mbhconv,mrot,mshift,mexpdhw,mexpdhd,mwcut,mmulh,mmulxh,mmach,mmrdh,mqmulh,mqmulxh,mqmach,mcpx,mqcpx,mcut,mclracc,mclracca,mdunpackh,mbhconve,mrdacc,mwtacc,maddacc,mdaddacc,mabsh,mdrot,mcpl,mdcut,mqsath,mset,m7,ccr,multi,unknown"
  (const_string "unknown"))



/* This is description of pipeline hazards based on DFA.  The
   following constructions can be used for this:

   o define_cpu_unit string [string]) describes a cpu functional unit
     (separated by comma).

     1st operand: Names of cpu function units.
     2nd operand: Name of automaton (see comments for
     DEFINE_AUTOMATON).

     All define_reservations and define_cpu_units should have unique
     names which can not be "nothing".

   o (exclusion_set string string) means that each CPU function unit
     in the first string can not be reserved simultaneously with each
     unit whose name is in the second string and vise versa.  CPU
     units in the string are separated by commas. For example, it is
     useful for description CPU with fully pipelined floating point
     functional unit which can execute simultaneously only single
     floating point insns or only double floating point insns.

   o (presence_set string string) means that each CPU function unit in
     the first string can not be reserved unless at least one of units
     whose names are in the second string is reserved.  This is an
     asymmetric relation.  CPU units in the string are separated by
     commas.  For example, it is useful for description that slot1 is
     reserved after slot0 reservation for a VLIW processor.

   o (absence_set string string) means that each CPU function unit in
     the first string can not be reserved only if each unit whose name
     is in the second string is not reserved.  This is an asymmetric
     relation (actually exclusion set is analogous to this one but it
     is symmetric).  CPU units in the string are separated by commas.
     For example, it is useful for description that slot0 can not be
     reserved after slot1 or slot2 reservation for a VLIW processor.

   o (define_bypass number out_insn_names in_insn_names) names bypass with
     given latency (the first number) from insns given by the first
     string (see define_insn_reservation) into insns given by the
     second string.  Insn names in the strings are separated by
     commas.

   o (define_automaton string) describes names of an automaton
     generated and used for pipeline hazards recognition.  The names
     are separated by comma.  Actually it is possibly to generate the
     single automaton but unfortunately it can be very large.  If we
     use more one automata, the summary size of the automata usually
     is less than the single one.  The automaton name is used in
     define_cpu_unit.  All automata should have unique names.

   o (define_reservation string string) names reservation (the first
     string) of cpu functional units (the 2nd string).  Sometimes unit
     reservations for different insns contain common parts.  In such
     case, you describe common part and use one its name (the 1st
     parameter) in regular expression in define_insn_reservation.  All
     define_reservations, define results and define_cpu_units should
     have unique names which can not be "nothing".

   o (define_insn_reservation name default_latency condition regexpr)
     describes reservation of cpu functional units (the 3nd operand)
     for instruction which is selected by the condition (the 2nd
     parameter).  The first parameter is used for output of debugging
     information.  The reservations are described by a regular
     expression according the following syntax:

       regexp = regexp "," oneof
              | oneof

       oneof = oneof "|" allof
             | allof

       allof = allof "+" repeat
             | repeat

       repeat = element "*" number
              | element

       element = cpu_function_name
               | reservation_name
               | result_name
               | "nothing"
               | "(" regexp ")"

       1. "," is used for describing start of the next cycle in
          reservation.

       2. "|" is used for describing the reservation described by the
          first regular expression *or* the reservation described by
          the second regular expression *or* etc.

       3. "+" is used for describing the reservation described by the
          first regular expression *and* the reservation described by
          the second regular expression *and* etc.

       4. "*" is used for convinience and simply means sequence in
          which the regular expression are repeated NUMBER times with
          cycle advancing (see ",").

       5. cpu function unit name which means reservation.

       6. reservation name -- see define_reservation.

       7. string "nothing" means no units reservation.

*/

(define_automaton "nodiv, idiv, div")

;; An FR500 packet can contain a single control instruction or a sequence
;; of up to four operations matching the regular expression:

;;	(I FM? I? FM? | FM? FM?) B? B?

;; where I denotes an integer operation, FM a floating-point or media
;; operation, and B a branch operation.  There are two units for each type
;; of instruction: I0 and I1, FM0 and FM1, and B0 and B1.  Units are
;; allocated left-to-right: the first integer instruction uses I0, the
;; second uses I1, and so on.

;; The FR400 is similar to the FR500 except that it allows only 2 operations
;; per packet and has only one branch unit.  We can use the FR500 conflict
;; description for the FR400, but need to define different cpu_units
;; later.

;; Slot/unit combinations available on the FR400 and above:
(define_cpu_unit "sl0_i0, sl0_fm0, sl0_b0, sl0_c" "nodiv")
(define_cpu_unit "sl1_fm0, sl1_i1, sl1_fm1, sl1_b0" "nodiv")

;; These are available on the FR500 and above:
(define_cpu_unit "sl1_b1" "nodiv")
(define_cpu_unit "sl2_i1, sl2_fm1, sl2_b0, sl2_b1" "nodiv")
(define_cpu_unit "sl3_fm1, sl3_b0, sl3_b1"  "nodiv")

;; The following describes conlicts by slots
;; slot0
(exclusion_set "sl0_i0"  "sl0_fm0,sl0_b0,sl0_c")
(exclusion_set "sl0_fm0" "sl0_b0,sl0_c")
(exclusion_set "sl0_b0"  "sl0_c")

;; slot1
(exclusion_set "sl1_fm0" "sl1_i1,sl1_fm1,sl1_b0,sl1_b1")
(exclusion_set "sl1_i1"  "sl1_fm1,sl1_b0,sl1_b1")
(exclusion_set "sl1_fm1" "sl1_b0,sl1_b1")
(exclusion_set "sl1_b0"  "sl1_b1")

;; slot2
(exclusion_set "sl2_i1"  "sl2_fm1,sl2_b0,sl2_b1")
(exclusion_set "sl2_fm1" "sl2_b0,sl2_b1")
(exclusion_set "sl2_b0"  "sl2_b1")

;; slot3
(exclusion_set "sl3_fm1" "sl3_b0,sl3_b1")
(exclusion_set "sl3_b0"  "sl3_b1")

;; The following describes conlicts by units
;; fm0
(exclusion_set "sl0_fm0" "sl1_fm0")

;; b0
(exclusion_set "sl0_b0"  "sl1_b0,sl2_b0,sl3_b0")
(exclusion_set "sl1_b0"  "sl2_b0,sl3_b0")
(exclusion_set "sl2_b0"  "sl3_b0")

;; i1
(exclusion_set "sl1_i1"  "sl2_i1")

;; fm1
(exclusion_set "sl1_fm1" "sl2_fm1,sl3_fm1")
(exclusion_set "sl2_fm1" "sl3_fm1")

;; b1
(exclusion_set "sl1_b1"  "sl2_b1,sl3_b1")
(exclusion_set "sl2_b1"  "sl3_b1")

;; The following describes remaining combinations of conflicts
;; slot0
(exclusion_set "sl0_i0"  "sl1_fm1,sl1_b1")
(exclusion_set "sl0_fm0" "sl1_i1,sl1_b1,sl2_i1,sl2_fm1,sl3_fm1,sl3_b0")
(exclusion_set "sl0_b0"  "sl1_fm0,sl1_i1,sl1_fm1,sl2_i1,sl2_fm1,sl2_b1,\
                          sl3_fm1,sl3_b1")
(exclusion_set "sl0_c"   "sl1_fm0,sl1_i1,sl1_fm1,sl1_b0,sl1_b1,sl2_i1,sl2_fm1,\
                          sl2_b0,sl2_b1,sl3_fm1,sl3_b0,sl3_b1")


;; slot1
(exclusion_set "sl1_fm0" "sl2_b1")
(exclusion_set "sl1_i1"  "sl2_fm1,sl2_b1,sl3_fm1,sl3_b0")
(exclusion_set "sl1_fm1" "sl2_i1,sl2_b1,sl3_b0")
(exclusion_set "sl1_b0"  "sl2_i1,sl2_fm1,sl3_fm1,sl3_b1")
(exclusion_set "sl1_b1"  "sl2_i1,sl2_fm1,sl2_b0,sl3_fm1,sl3_b0")

;; slot2
(exclusion_set "sl2_i1"  "sl3_b1")
(exclusion_set "sl2_fm1" "sl3_b1")
(exclusion_set "sl2_b0"  "sl3_fm1")
(exclusion_set "sl2_b1"  "sl3_fm1,sl3_b0")

;; slot3
(exclusion_set "sl1_fm0" "sl2_i1,sl2_fm1,sl2_b0,sl2_b1,sl3_fm1,sl3_b0,sl3_b1")
(exclusion_set "sl3_fm1" "sl2_i1,sl2_fm1,sl2_b0,sl2_b1,sl3_b0,sl3_b1")

;; ::::::::::::::::::::
;; ::
;; :: Generic/FR500 scheduler description
;; ::
;; ::::::::::::::::::::

;; Define reservation in order to describe only in terms of units.

(define_reservation "i0" "sl0_i0")
(define_reservation "f0" "sl0_fm0|sl1_fm0")
(define_reservation "m0" "f0")
(define_reservation "b0" "sl0_b0|sl1_b0|sl2_b0|sl3_b0")
(define_reservation "c"  "sl0_c")
(define_reservation "i1" "sl1_i1|sl2_i1")
(define_reservation "f1" "sl1_fm1|sl2_fm1|sl3_fm1")
(define_reservation "m1" "f1")
(define_reservation "b1" "sl1_b1|sl2_b1|sl3_b1")

;; Integer insns
;; It is not possibly to issue load & store in one VLIW insn.
(define_cpu_unit "idiv1" "idiv")
(define_cpu_unit "idiv2" "idiv")
(define_cpu_unit "l0"    "nodiv")
(define_cpu_unit "l1"    "nodiv")
(define_cpu_unit "s0"    "nodiv")

(exclusion_set "l1,l0" "s0")

;; We set the default_latency of sethi to be 0 to allow sethi and setlo to be
;; combined in the same VLIW instruction as allowed by the architecture.  This
;; assumes the only use of sethi is always followed by a setlo of the same
;; register.
(define_insn_reservation "i1_sethi" 0
  (and (eq_attr "cpu" "generic,fr500,tomcat")
       (eq_attr "type" "sethi"))
  "i0|i1")

(define_insn_reservation "i1_setlo" 1
  (and (eq_attr "cpu" "generic,fr500,tomcat")
       (eq_attr "type" "setlo"))
  "i0|i1")

(define_insn_reservation "i1_int" 1
  (and (eq_attr "cpu" "generic,fr500,tomcat")
       (eq_attr "type" "int"))
  "i0|i1")

(define_insn_reservation "i1_mul" 3
  (and (eq_attr "cpu" "generic,fr500,tomcat")
       (eq_attr "type" "mul"))
  "i0|i1")

(define_insn_reservation "i1_div" 19
  (and (eq_attr "cpu" "generic,fr500,tomcat")
       (eq_attr "type" "div"))
  "(i0|i1),(idiv1*18|idiv2*18)")

(define_insn_reservation "i2_gload" 4
  (and (eq_attr "cpu" "generic,fr500,tomcat")
       (eq_attr "type" "gload"))
  "(i0|i1)+(l0|l1)")

(define_insn_reservation "i2_fload" 4
  (and (eq_attr "cpu" "generic,fr500,tomcat")
       (eq_attr "type" "fload"))
  "(i0|i1)+(l0|l1)")

(define_insn_reservation "i3_gstore" 0
  (and (eq_attr "cpu" "generic,fr500,tomcat")
       (eq_attr "type" "gstore"))
  "i0+s0")

(define_insn_reservation "i3_fstore" 0
  (and (eq_attr "cpu" "generic,fr500,tomcat")
       (eq_attr "type" "fstore"))
  "i0+s0")

(define_insn_reservation "i4_move_gf" 3
  (and (eq_attr "cpu" "generic,fr500,tomcat")
       (eq_attr "type" "movgf"))
  "i0")

(define_insn_reservation "i4_move_fg" 3 
  (and (eq_attr "cpu" "generic,fr500,tomcat")
       (eq_attr "type" "movfg"))
  "i0")

(define_insn_reservation "i5" 0
  (and (eq_attr "cpu" "generic,fr500,tomcat")
       (eq_attr "type" "jumpl"))
  "i0")

;; Clear/commit is not generated now:
(define_insn_reservation "i6" 0 (const_int 0) "i0|i1")

;;
;; Branch-instructions
;;
(define_insn_reservation "b1/b3" 0
  (and (eq_attr "cpu" "generic,fr500,tomcat")
       (eq_attr "type" "jump,branch,ccr"))
  "b0|b1")

;; The following insn is not generated now.

(define_insn_reservation "b2" 0 (const_int 0) "b0")

(define_insn_reservation "b4" 0
  (and (eq_attr "cpu" "generic,fr500,tomcat")
       (eq_attr "type" "call"))
  "b0")

;; The following insns are not generated now.
(define_insn_reservation "b5" 0 (const_int 0) "b0|b1")
(define_insn_reservation "b6" 0 (const_int 0) "b0|b1")

;; Control insns
(define_insn_reservation "trap" 0
  (and (eq_attr "cpu" "generic,fr500,tomcat")
       (eq_attr "type" "trap"))
  "c")

(define_insn_reservation "control" 0
  (and (eq_attr "cpu" "generic,fr500,tomcat")
       (eq_attr "type" "spr"))
  "c")

;; Floating point insns
(define_cpu_unit "add0" "nodiv")
(define_cpu_unit "add1" "nodiv")
(define_cpu_unit "mul0" "nodiv")
(define_cpu_unit "mul1" "nodiv")
(define_cpu_unit "div1" "div")
(define_cpu_unit "div2" "div")
(define_cpu_unit "root" "div")

(define_bypass 4 "f1" "m1,m2,m3,m4,m5,m6,m7")
(define_insn_reservation "f1" 3
  (and (eq_attr "cpu" "generic,fr500,tomcat")
       (eq_attr "type" "fsconv,fdconv"))
  "(f0|f1)")

(define_bypass 4 "f2" "m1,m2,m3,m4,m5,m6,m7")
(define_insn_reservation "f2" 3
  (and (eq_attr "cpu" "generic,fr500,tomcat")
       (eq_attr "type" "fsadd,fdadd"))
  "(f0|f1)+(add0|add1)")

(define_bypass 4 "f3" "m1,m2,m3,m4,m5,m6,m7")
(define_insn_reservation "f3" 3
  (and (eq_attr "cpu" "generic,fr500,tomcat")
       (eq_attr "type" "fsmul,fdmul"))
  "(f0|f1)+(mul0|mul1)")

(define_bypass 11 "f4_div" "m1,m2,m3,m4,m5,m6,m7")
(define_insn_reservation "f4_div" 10