fr30.md

linux下的gcc编译器

)

(define_peephole
  [(set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
	   (match_operand:SI 0 "low_register_operand" "l"))
   (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
           (match_operand:SI 1 "low_register_operand" "l"))
   (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
           (match_operand:SI 2 "low_register_operand" "l"))
   (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
           (match_operand:SI 3 "low_register_operand" "l"))]
  "fr30_check_multiple_regs (operands, 4, 1)"
  "stm0	(%0, %1, %2, %3)"
  [(set_attr "delay_type" "other")]
)

(define_peephole
  [(set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
	   (match_operand:SI 0 "low_register_operand" "l"))
   (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
           (match_operand:SI 1 "low_register_operand" "l"))
   (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
           (match_operand:SI 2 "low_register_operand" "l"))]
  "fr30_check_multiple_regs (operands, 3, 1)"
  "stm0	(%0, %1, %2)"
  [(set_attr "delay_type" "other")]
)

(define_peephole
  [(set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
	   (match_operand:SI 0 "low_register_operand" "l"))
   (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
           (match_operand:SI 1 "low_register_operand" "l"))]
  "fr30_check_multiple_regs (operands, 2, 1)"
  "stm0	(%0, %1)"
  [(set_attr "delay_type" "other")]
)

;;}}}
;;{{{ Floating Point Moves 

;; Note - Patterns for SF mode moves are compulsory, but
;; patterns for DF are optional, as GCC can synthesize them.

(define_expand "movsf"
  [(set (match_operand:SF 0 "general_operand" "")
	(match_operand:SF 1 "general_operand" ""))]
  ""
  "{
  if (!reload_in_progress && !reload_completed
      && memory_operand (operands[0], SFmode)
      && memory_operand (operands[1], SFmode))
    operands[1] = copy_to_mode_reg (SFmode, operands[1]);
  }"
)

(define_insn "*movsf_internal"
  [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,red,m,r")
	(match_operand:SF 1 "general_operand"      "Fn,i,rde,r,rm"))]
  ""
  "*
  {
    switch (which_alternative)
    {
    case 0: return   \"ldi:32\\t%1, %0\";
    case 1: if (TARGET_SMALL_MODEL)
	      return \"ldi:20\\t%1, %0\";
            else
	      return \"ldi:32\\t%1, %0\";
    case 2: return   \"mov   \\t%1, %0\";
    case 3: return   \"st    \\t%1, %0\";
    case 4: return   \"ld    \\t%1, %0\";
    default: abort ();	       
    }
  }"
  [(set (attr "length") (cond [(eq_attr "alternative" "0") (const_int 6)
			       (eq_attr "alternative" "1") 
			                (if_then_else (eq_attr "size" "small")
						      (const_int 4)
						      (const_int 6))]
			      (const_int 2)))]
)

(define_insn "*movsf_constant_store"
  [(set (match_operand:SF 0 "memory_operand"    "=m")
	(match_operand:SF 1 "immediate_operand" "F"))]
  ""
  "*
  {
  const char *    ldi_instr;
  const char *    tmp_reg;
  static char     buffer[100];

  ldi_instr = fr30_const_double_is_zero (operands[1])
	    ? ldi_instr = \"ldi:8\" : \"ldi:32\";

  tmp_reg = reg_names [COMPILER_SCRATCH_REGISTER];
  
  sprintf (buffer, \"%s\\t#%%1, %s\\t;\\n\\tst\\t%s, %%0\\t; Created by movsf_constant_store\",
    ldi_instr, tmp_reg, tmp_reg);

  return buffer;
  }"
  [(set_attr "length" "8")]
)

;;}}}

;;}}} 
;;{{{ Conversions 

;; Signed conversions from a smaller integer to a larger integer

(define_insn "extendqisi2"
  [(set (match_operand:SI 0 "register_operand"                "=r")
	(sign_extend:SI (match_operand:QI 1 "register_operand" "0")))]
  ""
  "extsb	%0"
)

(define_insn "extendhisi2"
  [(set (match_operand:SI 0 "register_operand"                "=r")
	(sign_extend:SI (match_operand:HI 1 "register_operand" "0")))]
  ""
  "extsh	%0"
)

;; Unsigned conversions from a smaller integer to a larger integer

(define_insn "zero_extendqisi2"
  [(set (match_operand:SI 0 "register_operand"                "=r")
	(zero_extend:SI (match_operand:QI 1 "register_operand" "0")))]
  ""
  "extub	%0"
)

(define_insn "zero_extendhisi2"
  [(set (match_operand:SI 0 "register_operand"                "=r")
	(zero_extend:SI (match_operand:HI 1 "register_operand" "0")))]
  ""
  "extuh	%0"
)

;;}}} 
;;{{{ Arithmetic 

;;{{{ Addition 

;; This is a special pattern just for adjusting the stack size.
(define_insn "add_to_stack"
  [(set (reg:SI 15)
	(plus:SI (reg:SI 15)
		 (match_operand:SI 0 "stack_add_operand" "i")))]
  ""
  "addsp	%0"
)

;; We need some trickery to be able to handle the addition of
;; large (ie outside +/- 16) constants.  We need to be able to
;; handle this because reload assumes that it can generate add
;; instructions with arbitary sized constants.
(define_expand "addsi3"
  [(set (match_operand:SI 0 "register_operand"           "")
	(plus:SI (match_operand:SI 1 "register_operand"  "")
		 (match_operand:SI 2 "nonmemory_operand" "")))]
  ""
  "{
  if (   GET_CODE (operands[2]) == REG
      || GET_CODE (operands[2]) == SUBREG)
    emit_insn (gen_addsi_regs (operands[0], operands[1], operands[2]));
  else if (GET_CODE (operands[2]) != CONST_INT)
    emit_insn (gen_addsi_big_int (operands[0], operands[1], operands[2]));
  else if (   (REGNO (operands[1]) != FRAME_POINTER_REGNUM)
           && (REGNO (operands[1]) != ARG_POINTER_REGNUM)
	   && (INTVAL (operands[2]) >= -16)
	   && (INTVAL (operands[2]) <= 15))
    emit_insn (gen_addsi_small_int (operands[0], operands[1], operands[2]));
  else
    emit_insn (gen_addsi_big_int (operands[0], operands[1], operands[2]));
  DONE;
  }"
)

(define_insn "addsi_regs"
  [(set (match_operand:SI 0 "register_operand"          "=r")
	(plus:SI (match_operand:SI 1 "register_operand" "%0")
		 (match_operand:SI 2 "register_operand"  "r")))]
  ""
  "addn	%2, %0"
)

;; Do not allow an eliminable register in the source register.  It
;; might be eliminated in favor of the stack pointer, probably
;; increasing the offset, and so rendering the instruction illegal.
(define_insn "addsi_small_int"
  [(set (match_operand:SI 0 "register_operand"              "=r,r")
	(plus:SI (match_operand:SI 1 "register_operand"      "0,0")
		 (match_operand:SI 2 "add_immediate_operand" "I,J")))]
  "   (REGNO (operands[1]) != FRAME_POINTER_REGNUM)
   && (REGNO (operands[1]) != ARG_POINTER_REGNUM)"
  "@
   addn	%2, %0
   addn2	%2, %0"
)

(define_expand "addsi_big_int"
  [(set (match_operand:SI 0 "register_operand"           "")
	(plus:SI (match_operand:SI 1 "register_operand"  "")
		 (match_operand:SI 2 "immediate_operand" "")))]
  ""
  "{
  /* Cope with the possibility that ops 0 and 1 are the same register.  */
  if (REGNO (operands[0]) == REGNO (operands[1]))
    {
      if (reload_in_progress || reload_completed)
        {
	  rtx reg = gen_rtx_REG (SImode, 0/*COMPILER_SCRATCH_REGISTER*/);
	  
	  emit_insn (gen_movsi (reg, operands[2]));
	  emit_insn (gen_addsi_regs (operands[0], operands[0], reg));
	}
      else
	{
	  operands[2] = force_reg (SImode, operands[2]);
	  emit_insn (gen_addsi_regs (operands[0], operands[0], operands[2]));
	}
    }
  else
    {
      emit_insn (gen_movsi (operands[0], operands[2]));
      emit_insn (gen_addsi_regs (operands[0], operands[0], operands[1]));
    }
  DONE;
  }"
)

(define_insn "*addsi_for_reload"
  [(set (match_operand:SI 0 "register_operand"         "=&r,r,r")
	(plus:SI (match_operand:SI 1 "register_operand"  "r,r,r")
		 (match_operand:SI 2 "immediate_operand" "L,M,n")))]
  "reload_in_progress || reload_completed"
  "@
  ldi:8\\t#%2, %0  \\n\\taddn\\t%1, %0
  ldi:20\\t#%2, %0 \\n\\taddn\\t%1, %0
  ldi:32\\t#%2, %0 \\n\\taddn\\t%1, %0"
  [(set_attr "length" "4,6,8")]
)

;;}}}
;;{{{ Subtraction 

(define_insn "subsi3"
  [(set (match_operand:SI 0 "register_operand"       "=r")
	(minus:SI (match_operand:SI 1 "register_operand" "0")
	          (match_operand:SI 2 "register_operand" "r")))]
  ""
  "subn	%2, %0"
)

;;}}}
;;{{{ Multiplication 

;; Signed multiplication producing 64 bit results from 32 bit inputs
(define_insn "mulsidi3"
  [(set (match_operand:DI 0 "register_operand"                             "=r")
	   (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "%r"))
		    (sign_extend:DI (match_operand:SI 2 "register_operand"  "r"))))
   (clobber (reg:CC 16))]
  ""
  "mul	%2, %1\\n\\tmov\\tmdh, %0\\n\\tmov\\tmdl, %p0"
  [(set_attr "length" "6")]
)

;; Unsigned multiplication producing 64 bit results from 32 bit inputs
(define_insn "umulsidi3"
  [(set (match_operand:DI 0 "register_operand"                             "=r")
	   (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%r"))
		    (zero_extend:DI (match_operand:SI 2 "register_operand"  "r"))))
   (clobber (reg:CC 16))]
  ""
  "mulu	%2, %1\\n\\tmov\\tmdh, %0\\n\\tmov\\tmdl, %p0"
  [(set_attr "length" "6")]
)

;; Signed multiplication producing 32 bit result from 16 bit inputs
(define_insn "mulhisi3"
  [(set (match_operand:SI 0 "register_operand"                             "=r")
	   (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%r"))
		    (sign_extend:SI (match_operand:HI 2 "register_operand"  "r"))))
   (clobber (reg:CC 16))]
  ""
  "mulh	%2, %1\\n\\tmov\\tmdl, %0"
  [(set_attr "length" "4")]
)

;; Unsigned multiplication producing 32 bit result from 16 bit inputs
(define_insn "umulhisi3"
  [(set (match_operand:SI 0 "register_operand"                             "=r")
	   (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%r"))
		    (zero_extend:SI (match_operand:HI 2 "register_operand"  "r"))))
   (clobber (reg:CC 16))]
  ""
  "muluh	%2, %1\\n\\tmov\\tmdl, %0"
  [(set_attr "length" "4")]
)

;; Signed multiplication producing 32 bit result from 32 bit inputs
(define_insn "mulsi3"
  [(set (match_operand:SI 0 "register_operand"             "=r")
	   (mult:SI (match_operand:SI 1 "register_operand" "%r")
		    (match_operand:SI 2 "register_operand"  "r")))
   (clobber (reg:CC 16))]
  ""
  "mul	%2, %1\\n\\tmov\\tmdl, %0"
  [(set_attr "length" "4")]
)

;;}}}
;;{{{ Negation 

(define_expand "negsi2"
  [(set (match_operand:SI 0 "register_operand"         "")
	(neg:SI (match_operand:SI 1 "register_operand" "")))]
  ""
  "{
  if (REGNO (operands[0]) == REGNO (operands[1]))
    {
      if (reload_in_progress || reload_completed)
        {
	  rtx reg = gen_rtx_REG (SImode, 0/*COMPILER_SCRATCH_REGISTER*/);
	  
	  emit_insn (gen_movsi (reg, GEN_INT (0)));
	  emit_insn (gen_subsi3 (reg, reg, operands[0]));
	  emit_insn (gen_movsi (operands[0], reg));
	}
      else
	{
	  rtx reg = gen_reg_rtx (SImode);
	
	  emit_insn (gen_movsi (reg, GEN_INT (0)));
	  emit_insn (gen_subsi3 (reg, reg, operands[0]));
	  emit_insn (gen_movsi (operands[0], reg));
	}
    }
  else
    {
      emit_insn (gen_movsi_internal (operands[0], GEN_INT (0)));
      emit_insn (gen_subsi3 (operands[0], operands[0], operands[1]));
    }
  DONE;
  }"
)

;;}}}

;;}}} 
;;{{{ Shifts 

;; Arithmetic Shift Left
(define_insn "ashlsi3"
  [(set (match_operand:SI 0 "register_operand"            "=r,r,r")
	(ashift:SI (match_operand:SI 1 "register_operand"  "0,0,0")
		   (match_operand:SI 2 "nonmemory_operand" "r,I,K")))
   (clobber (reg:CC 16))]
  ""
  "@
  lsl	%2, %0
  lsl	%2, %0
  lsl2	%x2, %0"
)

;; Arithmetic Shift Right
(define_insn "ashrsi3"
  [(set (match_operand:SI 0 "register_operand"              "=r,r,r")
	(ashiftrt:SI (match_operand:SI 1 "register_operand"  "0,0,0")
		     (match_operand:SI 2 "nonmemory_operand" "r,I,K")))
   (clobber (reg:CC 16))]
  ""
  "@
  asr	%2, %0
  asr	%2, %0
  asr2	%x2, %0"
)

;; Logical Shift Right
(define_insn "lshrsi3"
  [(set (match_operand:SI 0 "register_operand"              "=r,r,r")
	(lshiftrt:SI (match_operand:SI 1 "register_operand"  "0,0,0")
		     (match_operand:SI 2 "nonmemory_operand" "r,I,K")))
   (clobber (reg:CC 16))]
  ""
  "@
  lsr	%2, %0
  lsr	%2, %0
  lsr2	%x2, %0"
)

;;}}} 
;;{{{ Logical Operations 

;; Logical AND, 32 bit integers
(define_insn "andsi3"
  [(set (match_operand:SI 0 "register_operand"         "=r")
	(and:SI (match_operand:SI 1 "register_operand" "%r")
		(match_operand:SI 2 "register_operand"  "0")))
   (clobber (reg:CC 16))]
  ""
  "and	%1, %0"
)

;; Inclusive OR, 32 bit integers
(define_insn "iorsi3"
  [(set (match_operand:SI 0 "register_operand"         "=r")
	(ior:SI (match_operand:SI 1 "register_operand" "%r")
		(match_operand:SI 2 "register_operand"  "0")))
   (clobber (reg:CC 16))]
  ""
  "or	%1, %0"
)

;; Exclusive OR, 32 bit integers
(define_insn "xorsi3"
  [(set (match_operand:SI 0 "register_operand"         "=r")
	(xor:SI (match_operand:SI 1 "register_operand" "%r")
		(match_operand:SI 2 "register_operand"  "0")))
   (clobber (reg:CC 16))]
  ""
  "eor	%1, %0"
)

;; One's complement, 32 bit integers
(define_expand "one_cmplsi2"
  [(set (match_operand:SI 0 "register_operand"         "")
	(not:SI (match_operand:SI 1 "register_operand" "")))]
  ""
  "{
  if (REGNO (operands[0]) == REGNO (operands[1]))
    {
      if (reload_in_progress || reload_completed)
        {
	  rtx reg = gen_rtx_REG (SImode, 0/*COMPILER_SCRATCH_REGISTER*/);
	  
	  emit_insn (gen_movsi (reg, GEN_INT (-1)));
	  emit_insn (gen_xorsi3 (operands[0], operands[0], reg));
	}
      else
	{
	  rtx reg = gen_reg_rtx (SImode);
	
	  emit_insn (gen_movsi (reg, GEN_INT (-1)));
	  emit_insn (gen_xorsi3 (operands[0], operands[0], reg));
	}
    }
  else
    {
      emit_insn (gen_movsi_internal (operands[0], GEN_INT (-1)));
      emit_insn (gen_xorsi3 (operands[0], operands[1], operands[0]));
    }
  DONE;
  }"
)

;;}}} 
;;{{{ Comparisons 

;; Note, we store the operands in the comparison insns, and use them later
;; when generating the branch or scc operation.

;; First the routines called by the machine independent part of the compiler
(define_expand "cmpsi"
  [(set (reg:CC 16)
        (compare:CC (match_operand:SI 0 "register_operand"  "")
		    (match_operand:SI 1 "nonmemory_operand" "")))]
  ""
  "{
  fr30_compare_op0 = operands[0];
  fr30_compare_op1 = operands[1];
  DONE;
  }"
)