fr30.md

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;; FR30 machine description.
;; Copyright (C) 1998, 1999, 2000, 2002 Free Software Foundation, Inc.
;; Contributed by Cygnus Solutions.

;; This file is part of GNU CC.

;; GNU CC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 2, or (at your option)
;; any later version.

;; GNU CC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
;; GNU General Public License for more details.

;; You should have received a copy of the GNU General Public License
;; along with GNU CC; see the file COPYING.  If not, write to
;; the Free Software Foundation, 59 Temple Place - Suite 330,
;; Boston, MA 02111-1307, USA.

;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.

;;{{{ Attributes 

(define_attr "length" "" (const_int 2))

;; Used to distinguish between small memory model targets and big mode targets.

(define_attr "size" "small,big"
  (const (if_then_else (symbol_ref "TARGET_SMALL_MODEL")
		       (const_string "small")
		       (const_string "big"))))


;; Define an attribute to be used by the delay slot code.
;; An instruction by default is considered to be 'delyabable'
;; that is, it can be placed into a delay slot, but it is not
;; itself an delyaed branch type instruction.  An instruction
;; whoes type is 'delayed' is one which has a delay slot, and
;; an instruction whoes delay_type is 'other' is one which does
;; not have a delay slot, nor can it be placed into a delay slot.

(define_attr "delay_type" "delayable,delayed,other" (const_string "delayable"))

;;}}} 
;;{{{ Delay Slot Specifications 

(define_delay (eq_attr "delay_type" "delayed")
  [(and (eq_attr "delay_type" "delayable")
	(eq_attr "length" "2"))
   (nil)
   (nil)]
)

;;}}}
;;{{{ Moves 

;;{{{ Comment 

;; Wrap moves in define_expand to prevent memory->memory moves from being
;; generated at the RTL level, which generates better code for most machines
;; which can't do mem->mem moves.

;; If operand 0 is a `subreg' with mode M of a register whose own mode is wider
;; than M, the effect of this instruction is to store the specified value in
;; the part of the register that corresponds to mode M.  The effect on the rest
;; of the register is undefined.

;; This class of patterns is special in several ways.  First of all, each of
;; these names *must* be defined, because there is no other way to copy a datum
;; from one place to another.

;; Second, these patterns are not used solely in the RTL generation pass.  Even
;; the reload pass can generate move insns to copy values from stack slots into
;; temporary registers.  When it does so, one of the operands is a hard
;; register and the other is an operand that can need to be reloaded into a
;; register.

;; Therefore, when given such a pair of operands, the pattern must
;; generate RTL which needs no reloading and needs no temporary
;; registers--no registers other than the operands.  For example, if
;; you support the pattern with a `define_expand', then in such a
;; case the `define_expand' mustn't call `force_reg' or any other such
;; function which might generate new pseudo registers.

;; This requirement exists even for subword modes on a RISC machine
;; where fetching those modes from memory normally requires several
;; insns and some temporary registers.  Look in `spur.md' to see how
;; the requirement can be satisfied.

;; During reload a memory reference with an invalid address may be passed as an
;; operand.  Such an address will be replaced with a valid address later in the
;; reload pass.  In this case, nothing may be done with the address except to
;; use it as it stands.  If it is copied, it will not be replaced with a valid
;; address.  No attempt should be made to make such an address into a valid
;; address and no routine (such as `change_address') that will do so may be
;; called.  Note that `general_operand' will fail when applied to such an
;; address.
;;
;; The global variable `reload_in_progress' (which must be explicitly declared
;; if required) can be used to determine whether such special handling is
;; required.
;;
;; The variety of operands that have reloads depends on the rest of
;; the machine description, but typically on a RISC machine these can
;; only be pseudo registers that did not get hard registers, while on
;; other machines explicit memory references will get optional
;; reloads.
;;
;; If a scratch register is required to move an object to or from memory, it
;; can be allocated using `gen_reg_rtx' prior to reload.  But this is
;; impossible during and after reload.  If there are cases needing scratch
;; registers after reload, you must define `SECONDARY_INPUT_RELOAD_CLASS' and
;; perhaps also `SECONDARY_OUTPUT_RELOAD_CLASS' to detect them, and provide
;; patterns `reload_inM' or `reload_outM' to handle them.

;; The constraints on a `moveM' must permit moving any hard register to any
;; other hard register provided that `HARD_REGNO_MODE_OK' permits mode M in
;; both registers and `REGISTER_MOVE_COST' applied to their classes returns a
;; value of 2.

;; It is obligatory to support floating point `moveM' instructions
;; into and out of any registers that can hold fixed point values,
;; because unions and structures (which have modes `SImode' or
;; `DImode') can be in those registers and they may have floating
;; point members.

;; There may also be a need to support fixed point `moveM' instructions in and
;; out of floating point registers.  Unfortunately, I have forgotten why this
;; was so, and I don't know whether it is still true.  If `HARD_REGNO_MODE_OK'
;; rejects fixed point values in floating point registers, then the constraints
;; of the fixed point `moveM' instructions must be designed to avoid ever
;; trying to reload into a floating point register.

;;}}}
;;{{{ Push and Pop  

;; Push a register onto the stack
(define_insn "movsi_push"
  [(set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
	(match_operand:SI 0 "register_operand" "a"))]
  ""
  "st	%0, @-r15"
)

;; Pop a register off the stack
(define_insn "movsi_pop"
  [(set:SI (match_operand:SI 0 "register_operand" "=a")
	(mem:SI (post_inc:SI (reg:SI 15))))]
  ""
  "ld	@r15+, %0"
)

;;}}}
;;{{{ 1 Byte Moves 

(define_expand "movqi"
  [(set (match_operand:QI 0 "general_operand" "")
	(match_operand:QI 1 "general_operand" ""))]
  ""
  "
{
  if (!reload_in_progress
      && !reload_completed
      && GET_CODE (operands[0]) == MEM
      && (GET_CODE (operands[1]) == MEM
         || immediate_operand (operands[1], QImode)))
    operands[1] = copy_to_mode_reg (QImode, operands[1]);
}")

(define_insn "movqi_unsigned_register_load"
  [(set (match_operand:SI 0 "register_operand"              "=r")
	(zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
  ""
  "ldub	%1, %0"
)

(define_expand "movqi_signed_register_load"
  [(set (match_operand:SI 0 "register_operand"               "")
	(sign_extend:SI (match_operand:QI 1 "memory_operand" "")))]
  ""
  "
  emit_insn (gen_movqi_unsigned_register_load (operands[0], operands[1]));
  emit_insn (gen_extendqisi2 (operands[0], operands[0]));
  DONE;
  "
)

(define_insn "*movqi_internal"
  [(set (match_operand:QI 0 "nonimmediate_operand" "=r,red,m,r")
	(match_operand:QI 1 "general_operand"       "i,red,r,rm"))]
  ""
  "@
   ldi:8\\t#%A1, %0
   mov  \\t%1, %0
   stb  \\t%1, %0
   ldub \\t%1, %0"
)

;;}}}
;;{{{ 2 Byte Moves 

(define_expand "movhi"
  [(set (match_operand:HI 0 "general_operand" "")
	(match_operand:HI 1 "general_operand" ""))]
  ""
  "
{
  if (!reload_in_progress
      && !reload_completed
      && GET_CODE (operands[0]) == MEM
      && (GET_CODE (operands[1]) == MEM
	 || immediate_operand (operands[1], HImode)))
    operands[1] = copy_to_mode_reg (HImode, operands[1]);
}")

(define_insn "movhi_unsigned_register_load"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
  ""
  "lduh	%1, %0"
)

(define_expand "movhi_signed_register_load"
  [(set (match_operand:SI 0 "register_operand" "")
	(sign_extend:SI (match_operand:HI 1 "memory_operand" "")))]
  ""
  "
  emit_insn (gen_movhi_unsigned_register_load (operands[0], operands[1]));
  emit_insn (gen_extendhisi2 (operands[0], operands[0]));
  DONE;
  "
)

(define_insn "*movhi_internal"
  [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,red,m,r")
	(match_operand:HI 1 "general_operand"       "L,M,n,red,r,rm"))]
  ""
  "@
   ldi:8 \\t#%1, %0
   ldi:20\\t#%1, %0
   ldi:32\\t#%1, %0
   mov   \\t%1, %0
   sth   \\t%1, %0
   lduh  \\t%1, %0"
  [(set_attr "length" "*,4,6,*,*,*")]
)

;;}}}
;;{{{ 4 Byte Moves 

;; If the destination is a MEM and the source is a
;; MEM or an CONST_INT move the source into a register.
(define_expand "movsi"
  [(set (match_operand:SI 0 "nonimmediate_operand" "")
	(match_operand:SI 1 "general_operand" ""))]
  ""
  "{
  if (!reload_in_progress
      && !reload_completed
      && GET_CODE(operands[0]) == MEM
      && (GET_CODE (operands[1]) == MEM
	  || immediate_operand (operands[1], SImode)))
     operands[1] = copy_to_mode_reg (SImode, operands[1]);
  }"
)

;; We can do some clever tricks when loading certain immediate
;; values.  We implement these tricks as define_splits, rather
;; than putting the code into the define_expand "movsi" above,
;; because if we put them there, they will be evaluated at RTL
;; generation time and then the combiner pass will come along
;; and replace the multiple insns that have been generated with
;; the original, slower, load insns.  (The combiner pass only
;; cares about reducing the number of instructions, it does not
;; care about instruction lengths or speeds).  Splits are
;; evaluated after the combine pass and before the scheduling
;; passes, so that they are the perfect place to put this
;; intelligence.
;;
;; XXX we probably ought to implement these for QI and HI mode
;; loads as well.

;; If we are loading a small negative constant we can save space
;; and time by loading the positive value and then sign extending it.
(define_split
  [(set (match_operand:SI 0 "register_operand"  "")
	(match_operand:SI 1 "const_int_operand" ""))]
   "INTVAL (operands[1]) <= -1 && INTVAL (operands[1]) >= -128"
   [(set:SI (match_dup 0) (match_dup 1))
    (set:SI (match_dup 0) (sign_extend:SI (match_dup 2)))]
   "{
   operands[1] = GEN_INT (INTVAL (operands[1]) & 0xff);
   operands[2] = gen_lowpart (QImode, operands[0]);
   }"
)

;; If we are loading a large negative constant, one which does
;; not have any of its bottom 24 bit set, then we can save time
;; and space by loading the byte value and shifting it into place.
(define_split
  [(set (match_operand:SI 0 "register_operand"  "")
	(match_operand:SI 1 "const_int_operand" ""))]
   "(INTVAL (operands[1]) < 0) && ((INTVAL (operands[1]) & 0x00ffffff) == 0)"
   [(set:SI (match_dup 0) (match_dup 2))
    (parallel [(set:SI (match_dup 0) (ashift:SI (match_dup 0) (const_int 24)))
	       (clobber (reg:CC 16))])]
   "{
   HOST_WIDE_INT val = INTVAL (operands[1]);
   operands[2] = GEN_INT (val >> 24);
   }"
)

;; If we are loading a large positive constant, one which has bits
;; in the top byte set, but whoes set bits all lie within an 8 bit
;; range, then we can save time and space by loading the byte value
;; and shifting it into place.
(define_split
  [(set (match_operand:SI 0 "register_operand"  "")
	(match_operand:SI 1 "const_int_operand" ""))]
   "(INTVAL (operands[1]) > 0x00ffffff)
   && ((INTVAL (operands[1]) >> exact_log2 (INTVAL (operands[1]) & (- INTVAL (operands[1])))) < 0x100)"
   [(set:SI (match_dup 0) (match_dup 2))
    (parallel [(set:SI (match_dup 0) (ashift:SI (match_dup 0) (match_dup 3)))
	       (clobber (reg:CC 16))])]
   "{
   HOST_WIDE_INT val = INTVAL (operands[1]);
   int shift = exact_log2 (val & ( - val));
   operands[2] = GEN_INT (val >> shift);
   operands[3] = GEN_INT (shift);
   }"
)

;; When TARGET_SMALL_MODEL is defined we assume that all symbolic
;; values are addresses which will fit in 20 bits.

(define_insn "movsi_internal"
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,red,m,r")
	(match_operand:SI 1 "general_operand"       "L,M,n,i,rde,r,rm"))]
  ""
  "*
  {
    switch (which_alternative)
    {
    case 0: return   \"ldi:8 \\t#%1, %0\";
    case 1: return   \"ldi:20\\t#%1, %0\";
    case 2: return   \"ldi:32\\t#%1, %0\";
    case 3: if (TARGET_SMALL_MODEL)
	      return \"ldi:20\\t%1, %0\";
            else
	      return \"ldi:32\\t%1, %0\";
    case 4: return   \"mov   \\t%1, %0\";
    case 5: return   \"st    \\t%1, %0\";
    case 6: return   \"ld    \\t%1, %0\";
    default: abort ();	       
    }
  }"
  [(set (attr "length") (cond [(eq_attr "alternative" "1") (const_int 4)
			       (eq_attr "alternative" "2") (const_int 6)
			       (eq_attr "alternative" "3") 
			                (if_then_else (eq_attr "size" "small")
						      (const_int 4)
						      (const_int 6))]
			      (const_int 2)))]
)

;;}}}
;;{{{ 8 Byte Moves

;; Note - the FR30 does not have an 8 byte load/store instruction
;; but we have to support this pattern because some other patterns
;; (eg muldisi2) can produce a DImode result.
;; (This code is stolen from the M32R port.)

(define_expand "movdi"
  [(set (match_operand:DI 0 "general_operand" "")
	(match_operand:DI 1 "general_operand" ""))]
  ""
  "
  /* Everything except mem = const or mem = mem can be done easily.  */
  
  if (GET_CODE (operands[0]) == MEM)
    operands[1] = force_reg (DImode, operands[1]);
  ")

;; We use an insn and a split so that we can generate
;; RTL rather than text from fr30_move_double().

(define_insn "*movdi_insn"
  [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r,r,m,r")
	(match_operand:DI 1 "di_operand"               "r,m,r,nF"))]
  "register_operand (operands[0], DImode) || register_operand (operands[1], DImode)"
  "#"
  [(set_attr "length" "4,8,12,12")]
)

(define_split
  [(set (match_operand:DI 0 "nonimmediate_di_operand" "")
	(match_operand:DI 1 "di_operand" ""))]
  "reload_completed"
  [(match_dup 2)]
  "operands[2] = fr30_move_double (operands);")

;;}}}
;;{{{ Load & Store Multiple Registers 

;; The load multiple and store multiple patterns are implemented
;; as peepholes because the only time they are expected to occur
;; is during function prologues and epilogues.

(define_peephole
  [(set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
	   (match_operand:SI 0 "high_register_operand" "h"))
   (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
           (match_operand:SI 1 "high_register_operand" "h"))
   (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
           (match_operand:SI 2 "high_register_operand" "h"))
   (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
           (match_operand:SI 3 "high_register_operand" "h"))]
  "fr30_check_multiple_regs (operands, 4, 1)"
  "stm1	(%0, %1, %2, %3)"
  [(set_attr "delay_type" "other")]
)

(define_peephole
  [(set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
	   (match_operand:SI 0 "high_register_operand" "h"))
   (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
           (match_operand:SI 1 "high_register_operand" "h"))
   (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
           (match_operand:SI 2 "high_register_operand" "h"))]
  "fr30_check_multiple_regs (operands, 3, 1)"
  "stm1	(%0, %1, %2)"
  [(set_attr "delay_type" "other")]
)

(define_peephole
  [(set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
	   (match_operand:SI 0 "high_register_operand" "h"))
   (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
           (match_operand:SI 1 "high_register_operand" "h"))]
  "fr30_check_multiple_regs (operands, 2, 1)"
  "stm1	(%0, %1)"
  [(set_attr "delay_type" "other")]
)

(define_peephole
  [(set:SI (match_operand:SI 0 "high_register_operand" "h")
           (mem:SI (post_inc:SI (reg:SI 15))))
   (set:SI (match_operand:SI 1 "high_register_operand" "h")
           (mem:SI (post_inc:SI (reg:SI 15))))
   (set:SI (match_operand:SI 2 "high_register_operand" "h")
           (mem:SI (post_inc:SI (reg:SI 15))))
   (set:SI (match_operand:SI 3 "high_register_operand" "h")
           (mem:SI (post_inc:SI (reg:SI 15))))]
  "fr30_check_multiple_regs (operands, 4, 0)"
  "ldm1	(%0, %1, %2, %3)"
  [(set_attr "delay_type" "other")]
)

(define_peephole
  [(set:SI (match_operand:SI 0 "high_register_operand" "h")
           (mem:SI (post_inc:SI (reg:SI 15))))
   (set:SI (match_operand:SI 1 "high_register_operand" "h")
           (mem:SI (post_inc:SI (reg:SI 15))))
   (set:SI (match_operand:SI 2 "high_register_operand" "h")
           (mem:SI (post_inc:SI (reg:SI 15))))]
  "fr30_check_multiple_regs (operands, 3, 0)"
  "ldm1	(%0, %1, %2)"
  [(set_attr "delay_type" "other")]
)

(define_peephole
  [(set:SI (match_operand:SI 0 "high_register_operand" "h")
           (mem:SI (post_inc:SI (reg:SI 15))))
   (set:SI (match_operand:SI 1 "high_register_operand" "h")
           (mem:SI (post_inc:SI (reg:SI 15))))]
  "fr30_check_multiple_regs (operands, 2, 0)"
  "ldm1	(%0, %1)"
  [(set_attr "delay_type" "other")]