i370.md

linux下的gcc编译器

(define_insn "extendqihi2"
  [(set (match_operand:HI 0 "general_operand" "=d")
	(sign_extend:HI (match_operand:QI 1 "general_operand" "0m")))]
  ""
  "*
{
  check_label_emit ();
  CC_STATUS_SET (operands[0], operands[1]);
  if (REG_P (operands[1]))
    {
      mvs_check_page (0, 8, 0);
      return \"SLL	%0,24\;SRA	%0,24\";
    }
  if (s_operand (operands[1], GET_MODE (operands[1])))
    {
      mvs_check_page (0, 8, 0);
      return \"ICM	%0,8,%1\;SRA	%0,24\";
    }
  mvs_check_page (0, 12, 0);
  return \"IC	%0,%1\;SLL	%0,24\;SRA	%0,24\";
}"
   [(set_attr "length" "12")]
)

;
; zero_extendsidi2 instruction pattern(s).
;

(define_expand "zero_extendsidi2"
  [(set (match_operand:DI 0 "register_operand" "=d")
        (zero_extend:DI (match_operand:SI 1 "general_operand" "")))]
  ""
  "
{
      emit_insn (gen_rtx_SET (VOIDmode,
		  operand_subword (operands[0], 0, 1, DImode), operands[1]));
      emit_insn (gen_rtx_SET (VOIDmode, operands[0],
			gen_rtx_LSHIFTRT (DImode, operands[0],
				gen_rtx_CONST_INT (SImode, 32))));
  DONE;
}")

;
; zero_extendhisi2 instruction pattern(s).
;

(define_insn "zero_extendhisi2"
  [(set (match_operand:SI 0 "general_operand" "=d")
	(zero_extend:SI (match_operand:HI 1 "general_operand" "0")))]
  ""
  "*
{
  check_label_emit ();
  /* AND only sets zero/not-zero bits not the arithmetic bits ...  */
  CC_STATUS_INIT;
  mvs_check_page (0, 4, 4);
  return \"N	%1,=XL4'0000FFFF'\";
}"
   [(set_attr "length" "4")]
)

;
; zero_extendqisi2 instruction pattern(s).
;

(define_insn "zero_extendqisi2"
  [(set (match_operand:SI 0 "general_operand" "=d,&d")
	(zero_extend:SI (match_operand:QI 1 "general_operand" "0i,m")))]
  ""
  "*
{
  check_label_emit ();
  if (REG_P (operands[1]))
    {
      /* AND only sets zero/not-zero bits not the arithmetic bits ...  */
      CC_STATUS_INIT;
      mvs_check_page (0, 4, 4);
      return \"N	%0,=XL4'000000FF'\";
    }
  if (GET_CODE (operands[1]) == CONST_INT)
    {
      mvs_check_page (0, 4, 0);
      return \"LA	%0,%c1(0,0)\";
    }
  CC_STATUS_INIT;
  mvs_check_page (0, 8, 0);
  return \"SLR	%0,%0\;IC	%0,%1\";
}"
   [(set_attr "length" "8")]
)

;
; zero_extendqihi2 instruction pattern(s).
;

(define_insn "zero_extendqihi2"
  [(set (match_operand:HI 0 "general_operand" "=d,&d")
	(zero_extend:HI (match_operand:QI 1 "general_operand" "0i,m")))]
  ""
  "*
{
  check_label_emit ();
  if (REG_P (operands[1]))
    {
      /* AND only sets zero/not-zero bits not the arithmetic bits ...  */
      CC_STATUS_INIT;
      mvs_check_page (0, 4, 4);
      return \"N	%0,=XL4'000000FF'\";
    }
  if (GET_CODE (operands[1]) == CONST_INT)
    {
      mvs_check_page (0, 4, 0);
      return \"LA	%0,%c1(0,0)\";
    }
  CC_STATUS_INIT;
  mvs_check_page (0, 8, 0);
  return \"SLR	%0,%0\;IC	%0,%1\";
}"
   [(set_attr "length" "8")]
)

;
; truncsihi2 instruction pattern(s).
;

(define_insn "truncsihi2"
  [(set (match_operand:HI 0 "general_operand" "=d,m")
	(truncate:HI (match_operand:SI 1 "general_operand" "0,d")))]
  ""
  "*
{
  check_label_emit ();
  if (REG_P (operands[0]))
    {
      CC_STATUS_SET (operands[0], operands[1]);
      mvs_check_page (0, 8, 0);
      return \"SLL	%0,16\;SRA	%0,16\";
    }
  mvs_check_page (0, 4, 0);
  return \"STH	%1,%0\";
}"
   [(set_attr "length" "8")]
)

;
; fix_truncdfsi2 instruction pattern(s).
;

(define_insn "fix_truncdfsi2"
  [(set (match_operand:SI 0 "general_operand" "=d")
        (fix:SI (truncate:DF (match_operand:DF 1 "general_operand" "+f"))))
	(clobber (reg:DF 16))]
  ""
  "*
{
  check_label_emit ();
  CC_STATUS_INIT;
  if (REGNO (operands[1]) == 16)
    {
      mvs_check_page (0, 12, 8);
      return \"AD	0,=XL8'4F08000000000000'\;STD	0,140(,13)\;L	%0,144(,13)\";
    }
  mvs_check_page (0, 14, 8);
  return \"LDR	0,%1\;AD	0,=XL8'4F08000000000000'\;STD	0,140(,13)\;L	%0,144(,13)\";
}"
   [(set_attr "length" "14")]
)

;
; floatsidf2 instruction pattern(s).
;
; LE/370 mode uses the float field of the TCA.
;

(define_insn "floatsidf2"
  [(set (match_operand:DF 0 "general_operand" "=f")
        (float:DF (match_operand:SI 1 "general_operand" "d")))]
  ""
  "*
{
  check_label_emit ();
  CC_STATUS_INIT;
#ifdef TARGET_ELF_ABI
  mvs_check_page (0, 22, 12);
  return \"MVC  140(4,13),=XL4'4E000000'\;ST	%1,144(,13)\;XI	144(13),128\;LD	%0,140(,13)\;SD	%0,=XL8'4E00000080000000'\";
#else
  mvs_check_page (0, 16, 8);
  return \"ST	%1,508(,12)\;XI	508(12),128\;LD	%0,504(,12)\;SD	%0,=XL8'4E00000080000000'\";
#endif
}"
   [(set_attr "length" "22")]
)

;
; truncdfsf2 instruction pattern(s).
;

(define_insn "truncdfsf2"
  [(set (match_operand:SF 0 "general_operand" "=f")
        (float_truncate:SF (match_operand:DF 1 "general_operand" "f")))]
  ""
  "*
{
  check_label_emit ();
  mvs_check_page (0, 2, 0);
  return \"LRER	%0,%1\";
}"
   [(set_attr "length" "2")]
)

;
; extendsfdf2 instruction pattern(s).
; 

(define_insn "extendsfdf2"
  [(set (match_operand:DF 0 "general_operand" "=f")
        (float_extend:DF (match_operand:SF 1 "general_operand" "fmF")))]
  ""
  "*
{
  check_label_emit ();
  CC_STATUS_SET (0, const0_rtx);
  if (FP_REG_P (operands[1]))
    {
      if (REGNO (operands[0]) == REGNO (operands[1]))
	{
	  mvs_check_page (0, 10, 0);
	  return \"STE	%1,140(,13)\;SDR	%0,%0\;LE	%0,140(,13)\";
	}
      mvs_check_page (0, 4, 0);
      return \"SDR	%0,%0\;LER	%0,%1\";
    }
  mvs_check_page (0, 6, 0);
  return \"SDR	%0,%0\;LE	%0,%1\";
}"
   [(set_attr "length" "10")]
)

;;
;;- Add instructions.
;;

;
; adddi3 instruction pattern(s).
;
;
;(define_expand "adddi3"
;  [(set (match_operand:DI 0 "general_operand" "")
;	(plus:DI (match_operand:DI 1 "general_operand" "")
;		 (match_operand:DI 2 "general_operand" "")))]
;  ""
;  "
;{
;  rtx label = gen_label_rtx ();
;  rtx op0_high = operand_subword (operands[0], 0, 1, DImode);
;  rtx op0_low = gen_lowpart (SImode, operands[0]);
;	
;  emit_insn (gen_rtx_SET (VOIDmode, op0_high,
;		    gen_rtx_PLUS (SImode,
;			    operand_subword (operands[1], 0, 1, DImode),
;			    operand_subword (operands[2], 0, 1, DImode))));
;  emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
;	      gen_rtx_SET (VOIDmode, op0_low,
;		      gen_rtx_PLUS (SImode, gen_lowpart (SImode, operands[1]),
;			      gen_lowpart (SImode, operands[2]))),
;	      gen_rtx_USE (VOIDmode, gen_rtx_LABEL_REF (VOIDmode, label)))));
;  emit_insn (gen_rtx_SET (VOIDmode, op0_high,
;		    gen_rtx_PLUS (SImode, op0_high,
;			    gen_rtx_CONST_INT (SImode, 1))));
;  emit_label (label);
;  DONE;
;}")

(define_insn ""
  [(set (match_operand:SI 0 "general_operand" "=d")
	(plus:SI (match_operand:SI 1 "general_operand" "%0")
		 (match_operand:SI 2 "general_operand" "g")))
   (use (label_ref (match_operand 3 "" "")))
;   (clobber (reg:SI 14))
   ]
  ""
  "*
{
  int onpage;

  check_label_emit ();
  onpage = mvs_check_label (CODE_LABEL_NUMBER (operands[3]));
  if (REG_P (operands[2]))
    {
      if (!onpage)
	{
	  mvs_check_page (0, 8, 4);
	  return \"ALR	%0,%2\;L	14,=A(%l3)\;BCR	12,14\";
	}
      if (mvs_check_page (0, 6, 0))
	{
	  mvs_check_page (0, 2, 4);
	  return \"ALR	%0,%2\;L	14,=A(%l3)\;BCR	12,14\";
	}
      return \"ALR	%0,%2\;BC	12,%l3\";
    }
  if (!onpage)
    {
      mvs_check_page (0, 10, 4);
      return \"AL	%0,%2\;L	14,=A(%l3)\;BCR	12,14\";
    }
  if (mvs_check_page (0, 8 ,0))
    {
      mvs_check_page (0, 2, 4);
      return \"AL	%0,%2\;L	14,=A(%l3)\;BCR	12,14\";
    }
  return \"AL	%0,%2\;BC	12,%l3\";
}"
   [(set_attr "length" "10")]
)

;
; addsi3 instruction pattern(s).
;
; The following insn is used when it is known that operand one is an address,
; frame, stack or argument pointer, and operand two is a constant that is
; small enough to fit in the displacement field.
; Notice that we can't allow the frame pointer to used as a normal register
; because of this insn.
;

(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=d")
	(plus:SI (match_operand:SI 1 "general_operand" "%a")
		 (match_operand:SI 2 "immediate_operand" "J")))]
  "((REGNO (operands[1]) == FRAME_POINTER_REGNUM || REGNO (operands[1]) == ARG_POINTER_REGNUM || REGNO (operands[1]) == STACK_POINTER_REGNUM) && (unsigned) INTVAL (operands[2]) < 4096)"
  "*
{
  check_label_emit ();
  CC_STATUS_INIT;  /* add assumes CC but LA doesn't set CC */
  mvs_check_page (0, 4, 0);
  return \"LA	%0,%c2(,%1)\";
}"
   [(set_attr "length" "4")]
)

; This insn handles additions that are relative to the frame pointer.

(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=d")
         (plus:SI (match_operand:SI 1 "register_operand" "%a")
                  (match_operand:SI 2 "immediate_operand" "i")))]
  "REGNO (operands[1]) == FRAME_POINTER_REGNUM"
  "*
{
  check_label_emit ();
  if ((unsigned) INTVAL (operands[2]) < 4096)
    {
      CC_STATUS_INIT;  /* add assumes CC but LA doesn't set CC */
      mvs_check_page (0, 4, 0);
      return \"LA	%0,%c2(,%1)\";
    }
  if (REGNO (operands[1]) == REGNO (operands[0]))
    {
      CC_STATUS_INIT;
      mvs_check_page (0, 4, 0);
      return \"A	%0,%2\";
    }
  mvs_check_page (0, 6, 0);
  return \"L	%0,%2\;AR	%0,%1\";
}"
   [(set_attr "length" "6")]
)

;;
;; The CC status bits for the arithmetic instructions are handled
;; in the NOTICE_UPDATE_CC macro (yeah???) and so they do not need
;; to be set below.  They only need to be invalidated if *not* set 
;; (e.g. by BCTR) ... yeah I think that's right ...
;; 

(define_insn "addsi3"
  [(set (match_operand:SI 0 "general_operand" "=d")
	(plus:SI (match_operand:SI 1 "general_operand" "%0")
		 (match_operand:SI 2 "general_operand" "g")))]
  ""
  "*
{
  check_label_emit ();
  if (REG_P (operands[2]))
    {
      mvs_check_page (0, 2, 0);
      return \"AR	%0,%2\";
    }
  if (GET_CODE (operands[2]) == CONST_INT)
    {
      if (INTVAL (operands[2]) == -1)
	{
          CC_STATUS_INIT;  /* add assumes CC but BCTR doesn't set CC */
	  mvs_check_page (0, 2, 0);
	  return \"BCTR	%0,0\";
	}
    }
  mvs_check_page (0, 4, 0);
  return \"A	%0,%2\";
}"
   [(set_attr "length" "4")]
)

;
; addhi3 instruction pattern(s).
;

(define_insn "addhi3"
  [(set (match_operand:HI 0 "general_operand" "=d")
	(plus:HI (match_operand:HI 1 "general_operand" "%0")
		 (match_operand:HI 2 "general_operand" "dmi")))]
  ""
  "*
{
  check_label_emit ();
  if (REG_P (operands[2]))
    {
      mvs_check_page (0, 8, 0);
      return \"STH	%2,140(,13)\;AH	%0,140(,13)\";
    }
  if (GET_CODE (operands[2]) == CONST_INT)
    {
      if (INTVAL (operands[2]) == -1)
	{
          CC_STATUS_INIT;  /* add assumes CC but BCTR doesn't set CC */
	  mvs_check_page (0, 2, 0);
	  return \"BCTR	%0,0\";
	}
      mvs_check_page (0, 4, 0);
      return \"AH	%0,%H2\";
    }
  mvs_check_page (0, 4, 0);
  return \"AH	%0,%2\";
}"
   [(set_attr "length" "8")]
)

;
; addqi3 instruction pattern(s).
;

(define_insn "addqi3"
  [(set (match_operand:QI 0 "general_operand" "=d")
	(plus:QI (match_operand:QI 1 "general_operand" "%a")
		 (match_operand:QI 2 "general_operand" "ai")))]
  ""
  "*
{
  check_label_emit ();
  CC_STATUS_INIT;  /* add assumes CC but LA doesn't set CC */
  mvs_check_page (0, 4, 0);
  if (REG_P (operands[2]))
    return \"LA	%0,0(%1,%2)\";
  return \"LA	%0,%B2(,%1)\";
}"
   [(set_attr "length" "4")]
)

;
; adddf3 instruction pattern(s).
;

(define_insn "adddf3"
  [(set (match_operand:DF 0 "general_operand" "=f")
	(plus:DF (match_operand:DF 1 "general_operand" "%0")
		 (match_operand:DF 2 "general_operand" "fmF")))]
  ""
  "*
{
  check_label_emit ();
  if (FP_REG_P (operands[2]))
    {
      mvs_check_page (0, 2, 0);
      return \"ADR	%0,%2\";
    }
  mvs_check_page (0, 4, 0);
  return \"AD	%0,%2\";
}"
   [(set_attr "length" "4")]
)

;
; addsf3 instruction pattern(s).
;

(define_insn "addsf3"
  [(set (match_operand:SF 0 "general_operand" "=f")
	(plus:SF (match_operand:SF 1 "general_operand" "%0")
		 (match_operand:SF 2 "general_operand" "fmF")))]
  ""
  "*
{
  check_label_emit ();
  if (FP_REG_P (operands[2]))
    {
      mvs_check_page (0, 2, 0);
      return \"AER	%0,%2\";
    }
  mvs_check_page (0, 4, 0);
  return \"AE	%0,%2\";
}"
   [(set_attr "length" "4")]
)

;;
;;- Subtract instructions.
;;

;
; subdi3 instruction pattern(s).
;
;
;(define_expand "subdi3"
;  [(set (match_operand:DI 0 "general_operand" "")
;	(minus:DI (match_operand:DI 1 "general_operand" "")
;		  (match_operand:DI 2 "general_operand" "")))]
;  ""
;  "
;{
;  rtx label = gen_label_rtx ();
;  rtx op0_high = operand_subword (operands[0], 0, 1, DImode);
;  rtx op0_low = gen_lowpart (SImode, operands[0]);
;	
;  emit_insn (gen_rtx_SET (VOIDmode, op0_high,
;		    gen_rtx_MINUS (SImode,
;			      operand_subword (operands[1], 0, 1, DImode),
;			      operand_subword (operands[2], 0, 1, DImode))));
;  emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
;		    gen_rtx_SET (VOIDmode, op0_low,
;			      gen_rtx_MINUS (SImode,
;				      gen_lowpart (SImode, operands[1]),
;				      gen_lowpart (SImode, operands[2]))),
;		    gen_rtx_USE (VOIDmode,
;			      gen_rtx_LABEL_REF (VOIDmode, label)))));
;  emit_insn (gen_rtx_SET (VOIDmode, op0_high,
;		      gen_rtx_MINUS (SImode, op0_high,
;			      gen_rtx_CONST_INT (SImode, 1))));
;  emit_label (label);
;  DONE;
;}")

(define_insn ""
  [(set (match_operand:SI 0 "general_operand" "=d")