i370.h

linux下的gcc编译器

/* Definitions of target machine for GNU compiler.  System/370 version.
   Copyright (C) 1989, 1993, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002
   Free Software Foundation, Inc.
   Contributed by Jan Stein ([e-mail]).
   Modified for OS/390 LanguageEnvironment C by Dave Pitts ([e-mail])
   Hacked for Linux-ELF/390 by Linas Vepstas ([e-mail])

This file is part of GNU CC.

GNU CC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.

GNU CC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with GNU CC; see the file COPYING.  If not, write to
the Free Software Foundation, 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA.  */

#ifndef GCC_I370_H
#define GCC_I370_H

/* Target CPU builtins.  */
#define TARGET_CPU_CPP_BUILTINS()		\
  do						\
    {						\
      builtin_define_std ("GCC");		\
      builtin_define_std ("gcc");		\
      builtin_assert ("machine=i370");		\
      builtin_assert ("cpu=i370");		\
    }						\
  while (0)

/* Run-time compilation parameters selecting different hardware subsets.  */

extern int target_flags;

/* The sizes of the code and literals on the current page.  */

extern int mvs_page_code, mvs_page_lit;

/* The current page number and the base page number for the function.  */

extern int mvs_page_num, function_base_page;

/* The name of the current function.  */

extern char *mvs_function_name;

/* The length of the function name malloc'd area.  */

extern int mvs_function_name_length;

/* Compile using char instructions (mvc, nc, oc, xc).  On 4341 use this since
   these are more than twice as fast as load-op-store.
   On 3090 don't use this since load-op-store is much faster.  */

#define TARGET_CHAR_INSTRUCTIONS (target_flags & 1)

/* Default target switches */

#define TARGET_DEFAULT 1

/* Macro to define tables used to set the flags.  This is a list in braces
   of pairs in braces, each pair being { "NAME", VALUE }
   where VALUE is the bits to set or minus the bits to clear.
   An empty string NAME is used to identify the default VALUE.  */

#define TARGET_SWITCHES							\
{ { "char-instructions", 1, N_("Generate char instructions")},            \
  { "no-char-instructions", -1, N_("Do not generate char instructions")}, \
  { "", TARGET_DEFAULT, 0} }

#define OVERRIDE_OPTIONS  override_options ()

/* To use IBM supplied macro function prologue and epilogue, define the
   following to 1.  Should only be needed if IBM changes the definition
   of their prologue and epilogue.  */

#define MACROPROLOGUE 0
#define MACROEPILOGUE 0

/* Target machine storage layout */

/* Define this if most significant bit is lowest numbered in instructions
   that operate on numbered bit-fields.  */

#define BITS_BIG_ENDIAN 1

/* Define this if most significant byte of a word is the lowest numbered.  */

#define BYTES_BIG_ENDIAN 1

/* Define this if MS word of a multiword is the lowest numbered.  */

#define WORDS_BIG_ENDIAN 1

/* Width of a word, in units (bytes).  */

#define UNITS_PER_WORD 4

/* Allocation boundary (in *bits*) for storing pointers in memory.  */

#define POINTER_BOUNDARY 32

/* Allocation boundary (in *bits*) for storing arguments in argument list.  */

#define PARM_BOUNDARY 32

/* Boundary (in *bits*) on which stack pointer should be aligned.  */

#define STACK_BOUNDARY 32

/* Allocation boundary (in *bits*) for the code of a function.  */

#define FUNCTION_BOUNDARY 32

/* There is no point aligning anything to a rounder boundary than this.  */

#define BIGGEST_ALIGNMENT 64

/* Alignment of field after `int : 0' in a structure.  */

#define EMPTY_FIELD_BOUNDARY 32

/* Define this if move instructions will actually fail to work when given
   unaligned data.  */

#define STRICT_ALIGNMENT 0

/* Define target floating point format.  */

#define TARGET_FLOAT_FORMAT IBM_FLOAT_FORMAT

/* Define character mapping for cross-compiling.  */
/* but only define it if really needed, since otherwise it will break builds */

#ifdef TARGET_EBCDIC
#ifdef HOST_EBCDIC
#define MAP_CHARACTER(c) ((char)(c))
#else
#define MAP_CHARACTER(c) ((char)mvs_map_char (c))
#endif
#endif

#ifdef TARGET_HLASM
/* HLASM requires #pragma map.  */
#define REGISTER_TARGET_PRAGMAS(PFILE) \
  cpp_register_pragma (PFILE, 0, "map", i370_pr_map)
#endif /* TARGET_HLASM */

/* Define maximum length of page minus page escape overhead.  */

#define MAX_MVS_PAGE_LENGTH 4080

/* Define special register allocation order desired.  
   Don't fiddle with this.  I did, and I got all sorts of register 
   spill errors when compiling even relatively simple programs...
   I have no clue why ...
   E.g. this one is bad:
   { 0, 1, 2, 9, 8, 7, 6, 5, 10, 15, 14, 12, 3, 4, 16, 17, 18, 19, 11, 13 }
 */

#define REG_ALLOC_ORDER							\
{ 0, 1, 2, 3, 14, 15, 12, 10, 9, 8, 7, 6, 5, 4, 16, 17, 18, 19, 11, 13 }

/* Standard register usage.  */

/* Number of actual hardware registers.  The hardware registers are
   assigned numbers for the compiler from 0 to just below
   FIRST_PSEUDO_REGISTER.
   All registers that the compiler knows about must be given numbers,
   even those that are not normally considered general registers.
   For the 370, we give the data registers numbers 0-15,
   and the floating point registers numbers 16-19.  */

#define FIRST_PSEUDO_REGISTER 20

/* Define base and page registers.  */

#define BASE_REGISTER 3
#define PAGE_REGISTER 4

#ifdef TARGET_HLASM
/* 1 for registers that have pervasive standard uses and are not available
   for the register allocator.  These are registers that must have fixed,
   valid values stored in them for the entire length of the subroutine call,
   and must not in any way be moved around, jiggered with, etc. That is,
   they must never be clobbered, and, if clobbered, the register allocator 
   will never restore them back.
   
   We use five registers in this special way:
   -- R3 which is used as the base register
   -- R4 the page origin table pointer used to load R3,
   -- R11 the arg pointer.  
   -- R12 the TCA pointer
   -- R13 the stack (DSA) pointer

   A fifth register is also exceptional: R14 is used in many branch
   instructions to hold the target of the branch.  Technically, this
   does not qualify R14 as a register with a long-term meaning; it should
   be enough, theoretically, to note that these instructions clobber
   R14, and let the compiler deal with that.  In practice, however,
   the "clobber" directive acts as a barrier to optimization, and the
   optimizer appears to be unable to perform optimizations around branches.
   Thus, a much better strategy appears to give R14 a pervasive use;
   this eliminates it from the register pool witout hurting optimization.

   There are other registers which have special meanings, but its OK
   for them to get clobbered, since other allocator config below will
   make sure that they always have the right value.  These are for 
   example:
   -- R1 the returned structure pointer.
   -- R10 the static chain reg.
   -- R15 holds the value a subroutine returns.

   Notice that it is *almost* safe to mark R11 as available to the allocator.
   By marking it as a call_used_register, in most cases, the compiler
   can handle it being clobbered.  However, there are a few rare
   circumstances where the register allocator will allocate r11 and 
   also try to use it as the arg pointer ... thus it must be marked fixed.
   I think this is a bug, but I can't track it down...
 */

#define FIXED_REGISTERS 						\
{ 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0 }
/*0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 17 18 19*/

/* 1 for registers not available across function calls.  These must include
   the FIXED_REGISTERS and also any registers that can be used without being
   saved.
   The latter must include the registers where values are returned
   and the register where structure-value addresses are passed.
   NOTE: all floating registers are undefined across calls.  
*/

#define CALL_USED_REGISTERS 						\
{ 1, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1 }
/*0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 17 18 19*/

/* Return number of consecutive hard regs needed starting at reg REGNO
   to hold something of mode MODE.
   This is ordinarily the length in words of a value of mode MODE
   but can be less for certain modes in special long registers.  
   Note that DCmode (complex double) needs two regs.
*/
#endif /* TARGET_HLASM */

/* ================= */
#ifdef TARGET_ELF_ABI 
/* The Linux/ELF ABI uses the same register layout as the 
 * the MVS/OE version, with the following exceptions:
 * -- r12 (rtca) is not used.
 */

#define FIXED_REGISTERS 						\
{ 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0 }
/*0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 17 18 19*/

#define CALL_USED_REGISTERS 						\
{ 1, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 1 }
/*0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 17 18 19*/

#endif /* TARGET_ELF_ABI */
/* ================= */


#define HARD_REGNO_NREGS(REGNO, MODE) 					\
  ((REGNO) > 15 ? 							\
   ((GET_MODE_SIZE (MODE) + 2*UNITS_PER_WORD - 1) / (2*UNITS_PER_WORD)) :	\
   (GET_MODE_SIZE(MODE)+UNITS_PER_WORD-1) / UNITS_PER_WORD)

/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
   On the 370, the cpu registers can hold QI, HI, SI, SF and DF.  The
   even registers can hold DI.  The floating point registers can hold
   either SF, DF, SC or DC.  */

#define HARD_REGNO_MODE_OK(REGNO, MODE)					\
  ((REGNO) < 16 ? (((REGNO) & 1) == 0 || 				\
		  (((MODE) != DImode) && ((MODE) != DFmode)))		\
		: ((MODE) == SFmode || (MODE) == DFmode) ||		\
                   (MODE) == SCmode || (MODE) == DCmode)

/* Value is 1 if it is a good idea to tie two pseudo registers when one has
   mode MODE1 and one has mode MODE2.
   If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
   for any hard reg, then this must be 0 for correct output.  */

#define MODES_TIEABLE_P(MODE1, MODE2)					\
  (((MODE1) == SFmode || (MODE1) == DFmode)				\
   == ((MODE2) == SFmode || (MODE2) == DFmode))

/* Specify the registers used for certain standard purposes.
   The values of these macros are register numbers.  */

/* 370 PC isn't overloaded on a register.  */

/* #define PC_REGNUM */

/* Register to use for pushing function arguments.  */

#define STACK_POINTER_REGNUM 13

/* Base register for access to local variables of the function.  */

#define FRAME_POINTER_REGNUM 13

/* Value should be nonzero if functions must have frame pointers.
   Zero means the frame pointer need not be set up (and parms may be
   accessed via the stack pointer) in functions that seem suitable.
   This is computed in `reload', in reload1.c.  */

#define FRAME_POINTER_REQUIRED 1

/* Base register for access to arguments of the function.  */

#define ARG_POINTER_REGNUM 11

/* R10 is register in which static-chain is passed to a function.  
   Static-chaining is done when a nested function references as a global
   a stack variable of its parent: e.g.
        int parent_func (int arg) { 
             int x;                            // x is in parents stack
             void child_func (void) { x++: }   // child references x as global var
             ... 
        }
 */

#define STATIC_CHAIN_REGNUM 10

/* R1 is register in which address to store a structure value is passed to
   a function.  This is used only when returning 64-bit long-long in a 32-bit arch
   and when calling functions that return structs by value. e.g.
        typedef struct A_s { int a,b,c; } A_t;
        A_t fun_returns_value (void) { 
            A_t a; a.a=1; a.b=2 a.c=3;
            return a;
        } 
   In the above, the storage for the return value is in the callers stack, and 
   the R1 points at that mem location.
 */

#define STRUCT_VALUE_REGNUM 1

/* Define the classes of registers for register constraints in the
   machine description.  Also define ranges of constants.

   One of the classes must always be named ALL_REGS and include all hard regs.
   If there is more than one class, another class must be named NO_REGS
   and contain no registers.

   The name GENERAL_REGS must be the name of a class (or an alias for
   another name such as ALL_REGS).  This is the class of registers
   that is allowed by "g" or "r" in a register constraint.
   Also, registers outside this class are allocated only when
   instructions express preferences for them.

   The classes must be numbered in nondecreasing order; that is,
   a larger-numbered class must never be contained completely
   in a smaller-numbered class.

   For any two classes, it is very desirable that there be another
   class that represents their union.  */

enum reg_class
  {
    NO_REGS, ADDR_REGS, DATA_REGS,
    FP_REGS, ALL_REGS, LIM_REG_CLASSES
  };

#define GENERAL_REGS DATA_REGS
#define N_REG_CLASSES (int) LIM_REG_CLASSES

/* Give names of register classes as strings for dump file.  */

#define REG_CLASS_NAMES 						\
{ "NO_REGS", "ADDR_REGS", "DATA_REGS", "FP_REGS", "ALL_REGS" }

/* Define which registers fit in which classes.  This is an initializer for
   a vector of HARD_REG_SET of length N_REG_CLASSES.  */

#define REG_CLASS_CONTENTS {{0}, {0x0fffe}, {0x0ffff}, {0xf0000}, {0xfffff}}