📄 sh.h
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/* Definitions of target machine for GNU compiler for Hitachi / SuperH SH. Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. Contributed by Steve Chamberlain (sac@cygnus.com). Improved by Jim Wilson (wilson@cygnus.com).This file is part of GNU CC.GNU CC is free software; you can redistribute it and/or modifyit under the terms of the GNU General Public License as published bythe Free Software Foundation; either version 2, or (at your option)any later version.GNU CC is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; without even the implied warranty ofMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See theGNU General Public License for more details.You should have received a copy of the GNU General Public Licensealong with GNU CC; see the file COPYING. If not, write tothe Free Software Foundation, 59 Temple Place - Suite 330,Boston, MA 02111-1307, USA. */#ifndef GCC_SH_H#define GCC_SH_H#define TARGET_VERSION \ fputs (" (Hitachi SH)", stderr);/* Unfortunately, insn-attrtab.c doesn't include insn-codes.h. We can't include it here, because hconfig.h is also included by gencodes.c . *//* ??? No longer true. */extern int code_for_indirect_jump_scratch;#define TARGET_CPU_CPP_BUILTINS() \do { \ builtin_define ("__sh__"); \ builtin_assert ("cpu=sh"); \ builtin_assert ("machine=sh"); \ switch ((int) sh_cpu) \ { \ case PROCESSOR_SH1: \ builtin_define ("__sh1__"); \ break; \ case PROCESSOR_SH2: \ builtin_define ("__sh2__"); \ break; \ case PROCESSOR_SH3: \ builtin_define ("__sh3__"); \ builtin_define ("__SH3__"); \ if (TARGET_HARD_SH4) \ builtin_define ("__SH4_NOFPU__"); \ break; \ case PROCESSOR_SH3E: \ builtin_define (TARGET_HARD_SH4 ? "__SH4_SINGLE_ONLY__" : "__SH3E__"); \ break; \ case PROCESSOR_SH4: \ builtin_define (TARGET_FPU_SINGLE ? "__SH4_SINGLE__" : "__SH4__"); \ break; \ case PROCESSOR_SH5: \ { \ builtin_define_with_value ("__SH5__", \ TARGET_SHMEDIA64 ? "64" : "32", 0); \ builtin_define_with_value ("__SHMEDIA__", \ TARGET_SHMEDIA ? "1" : "0", 0); \ if (! TARGET_FPU_DOUBLE) \ builtin_define ("__SH4_NOFPU__"); \ } \ } \ if (TARGET_HITACHI) \ builtin_define ("__HITACHI__"); \ builtin_define (TARGET_LITTLE_ENDIAN \ ? "__LITTLE_ENDIAN__" : "__BIG_ENDIAN__"); \ if (flag_pic) \ { \ builtin_define ("__pic__"); \ builtin_define ("__PIC__"); \ } \ TARGET_OBJFMT_CPP_BUILTINS (); \} while (0)/* We can not debug without a frame pointer. *//* #define CAN_DEBUG_WITHOUT_FP */#define CONDITIONAL_REGISTER_USAGE do \{ \ int regno; \ for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno ++) \ if (! VALID_REGISTER_P (regno)) \ fixed_regs[regno] = call_used_regs[regno] = 1; \ /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. */ \ if (TARGET_SH5) \ call_used_regs[FIRST_GENERAL_REG + 8] \ = call_used_regs[FIRST_GENERAL_REG + 9] = 1; \ if (TARGET_SHMEDIA) \ { \ regno_reg_class[FIRST_GENERAL_REG] = GENERAL_REGS; \ CLEAR_HARD_REG_SET (reg_class_contents[FP0_REGS]); \ regno_reg_class[FIRST_FP_REG] = FP_REGS; \ } \ if (flag_pic) \ fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ /* Hitachi saves and restores mac registers on call. */ \ if (TARGET_HITACHI && ! TARGET_NOMACSAVE) \ { \ call_used_regs[MACH_REG] = 0; \ call_used_regs[MACL_REG] = 0; \ } \ for (regno = FIRST_FP_REG + (TARGET_LITTLE_ENDIAN != 0); \ regno <= LAST_FP_REG; regno += 2) \ SET_HARD_REG_BIT (reg_class_contents[DF_HI_REGS], regno); \ if (TARGET_SHMEDIA) \ { \ for (regno = FIRST_TARGET_REG; regno <= LAST_TARGET_REG; regno ++)\ if (! fixed_regs[regno] && call_used_regs[regno]) \ SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \ } \ else \ for (regno = FIRST_GENERAL_REG; regno <= LAST_GENERAL_REG; regno++) \ if (! fixed_regs[regno] && call_used_regs[regno]) \ SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \} while (0) /* ??? Need to write documentation for all SH options and add it to the invoke.texi file. *//* Run-time compilation parameters selecting different hardware subsets. */extern int target_flags;#define ISIZE_BIT (1<<1)#define DALIGN_BIT (1<<6)#define SH1_BIT (1<<8)#define SH2_BIT (1<<9)#define SH3_BIT (1<<10)#define SH3E_BIT (1<<11)#define HARD_SH4_BIT (1<<5)#define FPU_SINGLE_BIT (1<<7)#define SH4_BIT (1<<12)#define FMOVD_BIT (1<<4)#define SH5_BIT (1<<0)#define SPACE_BIT (1<<13)#define BIGTABLE_BIT (1<<14)#define RELAX_BIT (1<<15)#define USERMODE_BIT (1<<16)#define HITACHI_BIT (1<<22)#define NOMACSAVE_BIT (1<<23)#define PREFERGOT_BIT (1<<24)#define PADSTRUCT_BIT (1<<28)#define LITTLE_ENDIAN_BIT (1<<29)#define IEEE_BIT (1<<30)/* Nonzero if we should dump out instruction size info. */#define TARGET_DUMPISIZE (target_flags & ISIZE_BIT)/* Nonzero to align doubles on 64 bit boundaries. */#define TARGET_ALIGN_DOUBLE (target_flags & DALIGN_BIT)/* Nonzero if we should generate code using type 1 insns. */#define TARGET_SH1 (target_flags & SH1_BIT)/* Nonzero if we should generate code using type 2 insns. */#define TARGET_SH2 (target_flags & SH2_BIT)/* Nonzero if we should generate code using type 3 insns. */#define TARGET_SH3 (target_flags & SH3_BIT)/* Nonzero if we should generate code using type 3E insns. */#define TARGET_SH3E ((target_flags & SH3E_BIT) && (target_flags & SH1_BIT))/* Nonzero if the cache line size is 32. */#define TARGET_CACHE32 (target_flags & HARD_SH4_BIT || TARGET_SH5)/* Nonzero if we schedule for a superscalar implementation. */#define TARGET_SUPERSCALAR (target_flags & HARD_SH4_BIT)/* Nonzero if the target has separate instruction and data caches. */#define TARGET_HARVARD (target_flags & HARD_SH4_BIT)/* Nonzero if compiling for SH4 hardware (to be used for insn costs etc.) */#define TARGET_HARD_SH4 (target_flags & HARD_SH4_BIT)/* Nonzero if the default precision of th FPU is single */#define TARGET_FPU_SINGLE (target_flags & FPU_SINGLE_BIT)/* Nonzero if a double-precision FPU is available. */#define TARGET_FPU_DOUBLE (target_flags & SH4_BIT)/* Nonzero if an FPU is available. */#define TARGET_FPU_ANY (TARGET_SH3E || TARGET_FPU_DOUBLE)/* Nonzero if we should generate code using type 4 insns. */#define TARGET_SH4 ((target_flags & SH4_BIT) && (target_flags & SH1_BIT))/* Nonzero if we should generate code for a SH5 CPU (either ISA). */#define TARGET_SH5 (target_flags & SH5_BIT)/* Nonzero if we should generate code using the SHcompact instruction set and 32-bit ABI. */#define TARGET_SHCOMPACT (TARGET_SH5 && TARGET_SH1)/* Nonzero if we should generate code using the SHmedia instruction set and ABI. */#define TARGET_SHMEDIA (TARGET_SH5 && ! TARGET_SH1)/* Nonzero if we should generate code using the SHmedia ISA and 32-bit ABI. */#define TARGET_SHMEDIA32 (TARGET_SH5 && ! TARGET_SH1 \ && (target_flags & SH3E_BIT))/* Nonzero if we should generate code using the SHmedia ISA and 64-bit ABI. */#define TARGET_SHMEDIA64 (TARGET_SH5 && ! TARGET_SH1 \ && ! (target_flags & SH3E_BIT))/* Nonzero if we should generate code using SHmedia FPU instructions. */#define TARGET_SHMEDIA_FPU (TARGET_SHMEDIA && TARGET_FPU_DOUBLE)/* Nonzero if we should generate fmovd. */#define TARGET_FMOVD (target_flags & FMOVD_BIT)/* Nonzero if we respect NANs. */#define TARGET_IEEE (target_flags & IEEE_BIT)/* Nonzero if we should generate smaller code rather than faster code. */#define TARGET_SMALLCODE (target_flags & SPACE_BIT)/* Nonzero to use long jump tables. */#define TARGET_BIGTABLE (target_flags & BIGTABLE_BIT)/* Nonzero to generate pseudo-ops needed by the assembler and linker to do function call relaxing. */#define TARGET_RELAX (target_flags & RELAX_BIT)/* Nonzero if using Hitachi's calling convention. */#define TARGET_HITACHI (target_flags & HITACHI_BIT)/* Nonzero if not saving macl/mach when using -mhitachi */#define TARGET_NOMACSAVE (target_flags & NOMACSAVE_BIT)/* Nonzero if padding structures to a multiple of 4 bytes. This is incompatible with Hitachi's compiler, and gives unusual structure layouts which confuse programmers. ??? This option is not useful, but is retained in case there are people who are still relying on it. It may be deleted in the future. */#define TARGET_PADSTRUCT (target_flags & PADSTRUCT_BIT)/* Nonzero if generating code for a little endian SH. */#define TARGET_LITTLE_ENDIAN (target_flags & LITTLE_ENDIAN_BIT)/* Nonzero if we should do everything in userland. */#define TARGET_USERMODE (target_flags & USERMODE_BIT)/* Nonzero if we should prefer @GOT calls when generating PIC. */#define TARGET_PREFERGOT (target_flags & PREFERGOT_BIT)#define SELECT_SH1 (SH1_BIT)#define SELECT_SH2 (SH2_BIT | SELECT_SH1)#define SELECT_SH3 (SH3_BIT | SELECT_SH2)#define SELECT_SH3E (SH3E_BIT | FPU_SINGLE_BIT | SELECT_SH3)#define SELECT_SH4_NOFPU (HARD_SH4_BIT | SELECT_SH3)#define SELECT_SH4_SINGLE_ONLY (HARD_SH4_BIT | SELECT_SH3E)#define SELECT_SH4 (SH4_BIT|SH3E_BIT|HARD_SH4_BIT | SELECT_SH3)#define SELECT_SH4_SINGLE (FPU_SINGLE_BIT | SELECT_SH4)#define SELECT_SH5_64 (SH5_BIT | SH4_BIT)#define SELECT_SH5_64_NOFPU (SH5_BIT)#define SELECT_SH5_32 (SH5_BIT | SH4_BIT | SH3E_BIT)#define SELECT_SH5_32_NOFPU (SH5_BIT | SH3E_BIT)#define SELECT_SH5_COMPACT (SH5_BIT | SH4_BIT | SELECT_SH3E)#define SELECT_SH5_COMPACT_NOFPU (SH5_BIT | SELECT_SH3)/* Reset all target-selection flags. */#define TARGET_NONE -(SH1_BIT | SH2_BIT | SH3_BIT | SH3E_BIT | SH4_BIT \ | HARD_SH4_BIT | FPU_SINGLE_BIT | SH5_BIT)#define TARGET_SWITCHES \{ {"1", TARGET_NONE, "" }, \ {"1", SELECT_SH1, "" }, \ {"2", TARGET_NONE, "" }, \ {"2", SELECT_SH2, "" }, \ {"3", TARGET_NONE, "" }, \ {"3", SELECT_SH3, "" }, \ {"3e", TARGET_NONE, "" }, \ {"3e", SELECT_SH3E, "" }, \ {"4-single-only", TARGET_NONE, "" }, \ {"4-single-only", SELECT_SH4_SINGLE_ONLY, "" }, \ {"4-single", TARGET_NONE, "" }, \ {"4-single", SELECT_SH4_SINGLE, "" },\ {"4-nofpu", TARGET_NONE, "" }, \ {"4-nofpu", SELECT_SH4_NOFPU, "" },\ {"4", TARGET_NONE, "" }, \ {"4", SELECT_SH4, "" }, \ {"5-64media", TARGET_NONE, "" }, \ {"5-64media", SELECT_SH5_64, "Generate 64-bit SHmedia code" }, \ {"5-64media-nofpu", TARGET_NONE, "" }, \ {"5-64media-nofpu", SELECT_SH5_64_NOFPU, "Generate 64-bit FPU-less SHmedia code" }, \ {"5-32media", TARGET_NONE, "" }, \ {"5-32media", SELECT_SH5_32, "Generate 32-bit SHmedia code" }, \ {"5-32media-nofpu", TARGET_NONE, "" }, \ {"5-32media-nofpu", SELECT_SH5_32_NOFPU, "Generate 32-bit FPU-less SHmedia code" }, \ {"5-compact", TARGET_NONE, "" }, \ {"5-compact", SELECT_SH5_COMPACT, "Generate SHcompact code" }, \ {"5-compact-nofpu", TARGET_NONE, "" }, \ {"5-compact-nofpu", SELECT_SH5_COMPACT_NOFPU, "Generate FPU-less SHcompact code" }, \ {"b", -LITTLE_ENDIAN_BIT, "" }, \ {"bigtable", BIGTABLE_BIT, "" }, \ {"dalign", DALIGN_BIT, "" }, \ {"fmovd", FMOVD_BIT, "" }, \ {"hitachi", HITACHI_BIT, "" }, \ {"nomacsave", NOMACSAVE_BIT, "" }, \ {"ieee", IEEE_BIT, "" }, \ {"isize", ISIZE_BIT, "" }, \ {"l", LITTLE_ENDIAN_BIT, "" }, \ {"no-ieee", -IEEE_BIT, "" }, \ {"padstruct", PADSTRUCT_BIT, "" }, \ {"prefergot", PREFERGOT_BIT, "" }, \ {"relax", RELAX_BIT, "" }, \ {"space", SPACE_BIT, "" }, \ {"usermode", USERMODE_BIT, "" }, \ SUBTARGET_SWITCHES \ {"", TARGET_DEFAULT, "" } \}/* This are meant to be redefined in the host dependent files */#define SUBTARGET_SWITCHES/* This defaults us to big-endian. */#ifndef TARGET_ENDIAN_DEFAULT#define TARGET_ENDIAN_DEFAULT 0#endif#ifndef TARGET_CPU_DEFAULT#define TARGET_CPU_DEFAULT SELECT_SH1#endif#define TARGET_DEFAULT (TARGET_CPU_DEFAULT|TARGET_ENDIAN_DEFAULT)⌨️ 快捷键说明
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