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linux下的gcc编译器

	cmp/eq\\t%S1,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/ge\\t%S1,%S0\;cmp/hs\\t%R1,%R0\\n%,Ldi%=:
	cmp/pz\\t%S0"
  [(set_attr "length" "8,2")
   (set_attr "type" "arith3,mt_group")])

;; -------------------------------------------------------------------------
;; DImode unsigned integer comparisons
;; -------------------------------------------------------------------------

(define_insn "cmpgeudi_t"
  [(set (reg:SI T_REG)
	(geu:SI (match_operand:DI 0 "arith_reg_operand" "r")
		(match_operand:DI 1 "arith_reg_operand" "r")))]
  "TARGET_SH2"
  "cmp/eq\\t%S1,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/hs\\t%S1,%S0\;cmp/hs\\t%R1,%R0\\n%,Ldi%=:"
  [(set_attr "length" "8")
   (set_attr "type" "arith3")])

(define_insn "cmpgtudi_t"
  [(set (reg:SI T_REG)
	(gtu:SI (match_operand:DI 0 "arith_reg_operand" "r")
		(match_operand:DI 1 "arith_reg_operand" "r")))]
  "TARGET_SH2"
  "cmp/eq\\t%S1,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/hi\\t%S1,%S0\;cmp/hi\\t%R1,%R0\\n%,Ldi%=:"
  [(set_attr "length" "8")
   (set_attr "type" "arith3")])

(define_insn "cmpeqdi_media"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(eq:DI (match_operand:DI 1 "register_operand" "%r")
	       (match_operand:DI 2 "arith_reg_or_0_operand" "Nr")))]
  "TARGET_SHMEDIA"
  "cmpeq	%1, %N2, %0"
  [(set_attr "type" "cmp_media")])

(define_insn "cmpgtdi_media"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(gt:DI (match_operand:DI 1 "arith_reg_or_0_operand" "Nr")
	       (match_operand:DI 2 "arith_reg_or_0_operand" "rN")))]
  "TARGET_SHMEDIA"
  "cmpgt	%N1, %N2, %0"
  [(set_attr "type" "cmp_media")])

(define_insn "cmpgtudi_media"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(gtu:DI (match_operand:DI 1 "arith_reg_or_0_operand" "Nr")
		(match_operand:DI 2 "arith_reg_or_0_operand" "rN")))]
  "TARGET_SHMEDIA"
  "cmpgtu	%N1, %N2, %0"
  [(set_attr "type" "cmp_media")])

;; We save the compare operands in the cmpxx patterns and use them when
;; we generate the branch.

(define_expand "cmpdi"
  [(set (reg:SI T_REG)
	(compare (match_operand:DI 0 "arith_operand" "")
		 (match_operand:DI 1 "arith_operand" "")))]
  "TARGET_SH2 || TARGET_SHMEDIA"
  "
{
  sh_compare_op0 = operands[0];
  sh_compare_op1 = operands[1];
  DONE;
}")
;; -------------------------------------------------------------------------
;; Conditional move instructions
;; -------------------------------------------------------------------------

;; The insn names may seem reversed, but note that cmveq performs the move
;; if op1 == 0, and cmvne does it if op1 != 0.

(define_insn "movdicc_false"
  [(set (match_operand:DI 0 "arith_reg_dest" "=r")
	(if_then_else:DI (eq (match_operand:DI 1 "arith_reg_operand" "r")
			     (const_int 0))
	 (match_operand:DI 2 "arith_reg_or_0_operand" "rN")
	 (match_operand:DI 3 "arith_reg_operand" "0")))]
  "TARGET_SHMEDIA"
  "cmveq	%1, %N2, %0"
  [(set_attr "type" "arith_media")])

(define_insn "movdicc_true"
  [(set (match_operand:DI 0 "arith_reg_dest" "=r")
	(if_then_else:DI (ne (match_operand:DI 1 "arith_reg_operand" "r")
			     (const_int 0))
	 (match_operand:DI 2 "arith_reg_or_0_operand" "rN")
	 (match_operand:DI 3 "arith_reg_operand" "0")))]
  "TARGET_SHMEDIA"
  "cmvne	%1, %N2, %0"
  [(set_attr "type" "arith_media")])

(define_expand "movdicc"
  [(set (match_operand:DI 0 "register_operand" "")
	(if_then_else:DI (match_operand 1 "comparison_operator" "")
			 (match_operand:DI 2 "register_operand" "")
			 (match_operand:DI 3 "register_operand" "")))]
  "TARGET_SHMEDIA"
  "
{
  if ((GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)
      && GET_MODE (sh_compare_op0) == DImode
      && sh_compare_op1 == const0_rtx)
    operands[1] = gen_rtx (GET_CODE (operands[1]), VOIDmode,
			   sh_compare_op0, sh_compare_op1);
  else
    {
      rtx tmp;

      if (no_new_pseudos)
	FAIL;

      tmp = gen_reg_rtx (DImode);

      switch (GET_CODE (operands[1]))
	{
	case EQ:
	  emit_insn (gen_seq (tmp));
	  operands[1] = gen_rtx (NE, VOIDmode, tmp, const0_rtx);
	  break;

	case NE:
	  emit_insn (gen_seq (tmp));
	  operands[1] = gen_rtx (EQ, VOIDmode, tmp, const0_rtx);
	  break;

	case GT:
	  emit_insn (gen_sgt (tmp));
	  operands[1] = gen_rtx (NE, VOIDmode, tmp, const0_rtx);
	  break;

	case LT:
	  emit_insn (gen_slt (tmp));
	  operands[1] = gen_rtx (NE, VOIDmode, tmp, const0_rtx);
	  break;

	case GE:
	  emit_insn (gen_slt (tmp));
	  operands[1] = gen_rtx (EQ, VOIDmode, tmp, const0_rtx);
	  break;

	case LE:
	  emit_insn (gen_sgt (tmp));
	  operands[1] = gen_rtx (EQ, VOIDmode, tmp, const0_rtx);
	  break;

	case GTU:
	  emit_insn (gen_sgtu (tmp));
	  operands[1] = gen_rtx (NE, VOIDmode, tmp, const0_rtx);
	  break;

	case LTU:
	  emit_insn (gen_sltu (tmp));
	  operands[1] = gen_rtx (NE, VOIDmode, tmp, const0_rtx);
	  break;

	case GEU:
	  emit_insn (gen_sltu (tmp));
	  operands[1] = gen_rtx (EQ, VOIDmode, tmp, const0_rtx);
	  break;

	case LEU:
	  emit_insn (gen_sgtu (tmp));
	  operands[1] = gen_rtx (EQ, VOIDmode, tmp, const0_rtx);
	  break;

	case UNORDERED:
	  emit_insn (gen_sunordered (tmp));
	  operands[1] = gen_rtx (NE, VOIDmode, tmp, const0_rtx);
	  break;

	case ORDERED:
	  emit_insn (gen_sunordered (tmp));
	  operands[1] = gen_rtx (EQ, VOIDmode, tmp, const0_rtx);
	  break;

	case UNEQ:
	case UNGE:
	case UNGT:
	case UNLE:
	case UNLT:
	case LTGT:
	  FAIL;

	default:
	  abort ();
	}
    }
}")

;; -------------------------------------------------------------------------
;; Addition instructions
;; -------------------------------------------------------------------------

(define_expand "adddi3"
  [(set (match_operand:DI 0 "arith_reg_operand" "")
	(plus:DI (match_operand:DI 1 "arith_reg_operand" "")
		 (match_operand:DI 2 "arith_operand" "")))]
  ""
  "
{
  if (TARGET_SH1)
    {
      if (no_new_pseudos && ! arith_reg_operand (operands[2], DImode))
        FAIL;
      operands[2] = force_reg (DImode, operands[2]);
      emit_insn (gen_adddi3_compact (operands[0], operands[1], operands[2]));
      DONE;
    }
}")

(define_insn "*adddi3_media"
  [(set (match_operand:DI 0 "arith_reg_operand" "=r,r")
	(plus:DI (match_operand:DI 1 "arith_reg_operand" "%r,r")
		 (match_operand:DI 2 "arith_operand" "r,P")))]
  "TARGET_SHMEDIA"
  "@
	add	%1, %2, %0
	addi	%1, %2, %0"
  [(set_attr "type" "arith_media")])

(define_insn "adddi3z_media"
  [(set (match_operand:DI 0 "arith_reg_operand" "=r")
	(zero_extend:DI
	 (plus:SI (match_operand:SI 1 "extend_reg_operand" "r")
		  (match_operand:SI 2 "extend_reg_or_0_operand" "rN"))))]
  "TARGET_SHMEDIA"
  "addz.l	%1, %N2, %0"
  [(set_attr "type" "arith_media")])

(define_insn "adddi3_compact"
  [(set (match_operand:DI 0 "arith_reg_operand" "=r")
	(plus:DI (match_operand:DI 1 "arith_reg_operand" "%0")
		 (match_operand:DI 2 "arith_reg_operand" "r")))
   (clobber (reg:SI T_REG))]
  "TARGET_SH1"
  "#"
  [(set_attr "length" "6")])

(define_split
  [(set (match_operand:DI 0 "arith_reg_operand" "")
	(plus:DI (match_operand:DI 1 "arith_reg_operand" "")
		 (match_operand:DI 2 "arith_reg_operand" "")))
   (clobber (reg:SI T_REG))]
  "TARGET_SH1 && reload_completed"
  [(const_int 0)]
  "
{
  rtx high0, high2, low0 = gen_lowpart (SImode, operands[0]);
  high0 = gen_rtx_REG (SImode,
		       true_regnum (operands[0])
		       + (TARGET_LITTLE_ENDIAN ? 1 : 0));
  high2 = gen_rtx_REG (SImode,
		       true_regnum (operands[2])
		       + (TARGET_LITTLE_ENDIAN ? 1 : 0));
  emit_insn (gen_clrt ());
  emit_insn (gen_addc (low0, low0, gen_lowpart (SImode, operands[2])));
  emit_insn (gen_addc1 (high0, high0, high2));
  DONE;
}")

(define_insn "addc"
  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
	(plus:SI (plus:SI (match_operand:SI 1 "arith_reg_operand" "0")
			  (match_operand:SI 2 "arith_reg_operand" "r"))
		 (reg:SI T_REG)))
   (set (reg:SI T_REG)
	(ltu:SI (plus:SI (match_dup 1) (match_dup 2)) (match_dup 1)))]
  "TARGET_SH1"
  "addc	%2,%0"
  [(set_attr "type" "arith")])

(define_insn "addc1"
  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
	(plus:SI (plus:SI (match_operand:SI 1 "arith_reg_operand" "0")
			  (match_operand:SI 2 "arith_reg_operand" "r"))
		 (reg:SI T_REG)))
   (clobber (reg:SI T_REG))]
  "TARGET_SH1"
  "addc	%2,%0"
  [(set_attr "type" "arith")])

(define_expand "addsi3"
  [(set (match_operand:SI 0 "arith_reg_operand" "")
	(plus:SI (match_operand:SI 1 "arith_operand" "")
		 (match_operand:SI 2 "arith_operand" "")))]
  ""
  "
{
  if (TARGET_SHMEDIA)
    operands[1] = force_reg (SImode, operands[1]);
}")

(define_insn "addsi3_media"
  [(set (match_operand:SI 0 "arith_reg_operand" "=r,r")
	(plus:SI (match_operand:SI 1 "extend_reg_operand" "%r,r")
		 (match_operand:SI 2 "arith_operand" "r,P")))]
  "TARGET_SHMEDIA"
  "@
	add.l	%1, %2, %0
	addi.l	%1, %2, %0"
  [(set_attr "type" "arith_media")])

(define_insn "*addsi3_compact"
  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
	(plus:SI (match_operand:SI 1 "arith_operand" "%0")
		 (match_operand:SI 2 "arith_operand" "rI")))]
  "TARGET_SH1"
  "add	%2,%0"
  [(set_attr "type" "arith")])

;; -------------------------------------------------------------------------
;; Subtraction instructions
;; -------------------------------------------------------------------------

(define_expand "subdi3"
  [(set (match_operand:DI 0 "arith_reg_operand" "")
	(minus:DI (match_operand:DI 1 "arith_reg_or_0_operand" "")
		  (match_operand:DI 2 "arith_reg_operand" "")))]
  ""
  "
{
  if (TARGET_SH1)
    {
      operands[1] = force_reg (DImode, operands[1]);
      emit_insn (gen_subdi3_compact (operands[0], operands[1], operands[2]));
      DONE;
    }
}")

(define_insn "*subdi3_media"
  [(set (match_operand:DI 0 "arith_reg_operand" "=r")
	(minus:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rN")
		  (match_operand:DI 2 "arith_reg_operand" "r")))]
  "TARGET_SHMEDIA"
  "sub	%N1, %2, %0"
  [(set_attr "type" "arith_media")])

(define_insn "subdi3_compact"
  [(set (match_operand:DI 0 "arith_reg_operand" "=r")
	(minus:DI (match_operand:DI 1 "arith_reg_operand" "0")
		 (match_operand:DI 2 "arith_reg_operand" "r")))
   (clobber (reg:SI T_REG))]
  "TARGET_SH1"
  "#"
  [(set_attr "length" "6")])

(define_split
  [(set (match_operand:DI 0 "arith_reg_operand" "")
	(minus:DI (match_operand:DI 1 "arith_reg_operand" "")
		  (match_operand:DI 2 "arith_reg_operand" "")))
   (clobber (reg:SI T_REG))]
  "TARGET_SH1 && reload_completed"
  [(const_int 0)]
  "
{
  rtx high0, high2, low0 = gen_lowpart (SImode, operands[0]);
  high0 = gen_rtx_REG (SImode,
		       true_regnum (operands[0])
		       + (TARGET_LITTLE_ENDIAN ? 1 : 0));
  high2 = gen_rtx_REG (SImode,
		       true_regnum (operands[2])
		       + (TARGET_LITTLE_ENDIAN ? 1 : 0));
  emit_insn (gen_clrt ());
  emit_insn (gen_subc (low0, low0, gen_lowpart (SImode, operands[2])));
  emit_insn (gen_subc1 (high0, high0, high2));
  DONE;
}")

(define_insn "subc"
  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
	(minus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
			    (match_operand:SI 2 "arith_reg_operand" "r"))
		  (reg:SI T_REG)))
   (set (reg:SI T_REG)
	(gtu:SI (minus:SI (match_dup 1) (match_dup 2)) (match_dup 1)))]
  "TARGET_SH1"
  "subc	%2,%0"
  [(set_attr "type" "arith")])

(define_insn "subc1"
  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
	(minus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
			    (match_operand:SI 2 "arith_reg_operand" "r"))
		  (reg:SI T_REG)))
   (clobber (reg:SI T_REG))]
  "TARGET_SH1"