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linux下的gcc编译器

;;- Machine description for Hitachi / SuperH SH.
;;  Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
;;  2004 Free Software Foundation, Inc.
;;  Contributed by Steve Chamberlain ([e-mail]).
;;  Improved by Jim Wilson ([e-mail]).

;; This file is part of GNU CC.

;; GNU CC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 2, or (at your option)
;; any later version.

;; GNU CC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
;; GNU General Public License for more details.

;; You should have received a copy of the GNU General Public License
;; along with GNU CC; see the file COPYING.  If not, write to
;; the Free Software Foundation, 59 Temple Place - Suite 330,
;; Boston, MA 02111-1307, USA.


;; ??? Should prepend a * to all pattern names which are not used.
;; This will make the compiler smaller, and rebuilds after changes faster.

;; ??? Should be enhanced to include support for many more GNU superoptimizer
;; sequences.  Especially the sequences for arithmetic right shifts.

;; ??? Should check all DImode patterns for consistency and usefulness.

;; ??? The MAC.W and MAC.L instructions are not supported.  There is no
;; way to generate them.

;; ??? The cmp/str instruction is not supported.  Perhaps it can be used
;; for a str* inline function.

;; BSR is not generated by the compiler proper, but when relaxing, it
;; generates .uses pseudo-ops that allow linker relaxation to create
;; BSR.  This is actually implemented in bfd/{coff,elf32}-sh.c

;; Special constraints for SH machine description:
;;
;;    t -- T
;;    x -- mac
;;    l -- pr
;;    z -- r0
;;
;; Special formats used for outputting SH instructions:
;;
;;   %.  --  print a .s if insn needs delay slot
;;   %@  --  print rte/rts if is/isn't an interrupt function
;;   %#  --  output a nop if there is nothing to put in the delay slot
;;   %O  --  print a constant without the #
;;   %R  --  print the lsw reg of a double
;;   %S  --  print the msw reg of a double
;;   %T  --  print next word of a double REG or MEM
;;
;; Special predicates:
;;
;;  arith_operand          -- operand is valid source for arithmetic op
;;  arith_reg_operand      -- operand is valid register for arithmetic op
;;  general_movdst_operand -- operand is valid move destination
;;  general_movsrc_operand -- operand is valid move source
;;  logical_operand        -- operand is valid source for logical op

;; -------------------------------------------------------------------------
;; Constants
;; -------------------------------------------------------------------------

(define_constants [
  (AP_REG	145)
  (PR_REG	146)
  (T_REG	147)
  (GBR_REG	144)
  (MACH_REG	148)
  (MACL_REG	149)
  (FPUL_REG	150)
  (RAP_REG	152)

  (FPSCR_REG	151)

  (PIC_REG	12)
  (FP_REG	14)
  (SP_REG	15)

  (PR_MEDIA_REG	18)
  (T_MEDIA_REG	19)

  (R0_REG	0)
  (R1_REG	1)
  (R2_REG	2)
  (R3_REG	3)
  (R4_REG	4)
  (R5_REG	5)
  (R6_REG	6)
  (R7_REG	7)
  (R8_REG	8)
  (R9_REG	9)
  (R10_REG	10)
  (R20_REG	20)
  (R21_REG	21)
  (R22_REG	22)
  (R23_REG	23)

  (DR0_REG	64)
  (DR2_REG	66)
  (DR4_REG	68)
  (FR23_REG	87)

  (TR0_REG	128)
  (TR1_REG	129)
  (TR2_REG	130)

  (XD0_REG	136)

  ;; These are used with unspec.
  (UNSPEC_COMPACT_ARGS	0)
  (UNSPEC_MOVA		1)
  (UNSPEC_CASESI	2)
  (UNSPEC_DATALABEL	3)
  (UNSPEC_BBR		4)
  (UNSPEC_SFUNC		5)
  (UNSPEC_PIC		6)
  (UNSPEC_GOT		7)
  (UNSPEC_GOTOFF	8)
  (UNSPEC_PLT		9)
  (UNSPEC_CALLER	10)
  (UNSPEC_GOTPLT	11)
  (UNSPEC_ICACHE	12)
  (UNSPEC_INIT_TRAMP	13)
  (UNSPEC_FCOSA		14)
  (UNSPEC_FSRRA		15)
  (UNSPEC_FSINA		16)
  (UNSPEC_NSB		17)
  (UNSPEC_ALLOCO	18)

  ;; These are used with unspec_volatile.
  (UNSPECV_BLOCKAGE	0)
  (UNSPECV_ALIGN	1)
  (UNSPECV_CONST2	2)
  (UNSPECV_CONST4	4)
  (UNSPECV_CONST8	6)
  (UNSPECV_WINDOW_END	10)
  (UNSPECV_CONST_END	11)
])  

;; -------------------------------------------------------------------------
;; Attributes
;; -------------------------------------------------------------------------

;; Target CPU.

(define_attr "cpu"
 "sh1,sh2,sh3,sh3e,sh4,sh5"
  (const (symbol_ref "sh_cpu_attr")))

(define_attr "endian" "big,little"
 (const (if_then_else (symbol_ref "TARGET_LITTLE_ENDIAN")
		      (const_string "little") (const_string "big"))))

;; Indicate if the default fpu mode is single precision.
(define_attr "fpu_single" "yes,no"
  (const (if_then_else (symbol_ref "TARGET_FPU_SINGLE")
                         (const_string "yes") (const_string "no"))))

(define_attr "fmovd" "yes,no"
  (const (if_then_else (symbol_ref "TARGET_FMOVD")
		       (const_string "yes") (const_string "no"))))
;; pipeline model
(define_attr "pipe_model" "sh1,sh4,sh5media"
  (const
   (cond [(symbol_ref "TARGET_SHMEDIA") (const_string "sh5media")
          (symbol_ref "TARGET_SUPERSCALAR") (const_string "sh4")]
         (const_string "sh1"))))

;; cbranch	conditional branch instructions
;; jump		unconditional jumps
;; arith	ordinary arithmetic
;; arith3	a compound insn that behaves similarly to a sequence of
;;		three insns of type arith
;; arith3b	like above, but might end with a redirected branch
;; load		from memory
;; load_si	Likewise, SImode variant for general register.
;; fload	Likewise, but load to fp register.
;; store	to memory
;; move		general purpose register to register
;; mt_group	other sh4 mt instructions
;; fmove	register to register, floating point
;; smpy		word precision integer multiply
;; dmpy		longword or doublelongword precision integer multiply
;; return	rts
;; pload	load of pr reg, which can't be put into delay slot of rts
;; prset	copy register to pr reg, ditto
;; pstore	store of pr reg, which can't be put into delay slot of jsr
;; prget	copy pr to register, ditto
;; pcload	pc relative load of constant value
;; pcfload	Likewise, but load to fp register.
;; pcload_si	Likewise, SImode variant for general register.
;; rte		return from exception
;; sfunc	special function call with known used registers
;; call		function call
;; fp		floating point
;; fdiv		floating point divide (or square root)
;; gp_fpul	move from general purpose register to fpul
;; fpul_gp	move from fpul to general purpose register
;; mac_gp	move from mac[lh] to general purpose register
;; dfp_arith, dfp_cmp,dfp_conv
;; ftrc_s	fix_truncsfsi2_i4
;; dfdiv	double precision floating point divide (or square root)
;; cwb		ic_invalidate_line_i
;; arith_media	SHmedia arithmetic, logical, and shift instructions
;; cbranch_media SHmedia conditional branch instructions
;; cmp_media	SHmedia compare instructions
;; dfdiv_media	SHmedia double precision divide and square root
;; dfmul_media	SHmedia double precision multiply instruction
;; dfparith_media SHmedia double precision floating point arithmetic
;; dfpconv_media SHmedia double precision floating point conversions
;; dmpy_media	SHmedia longword multiply
;; fcmp_media	SHmedia floating point compare instructions
;; fdiv_media	SHmedia single precision divide and square root
;; fload_media	SHmedia floating point register load instructions
;; fmove_media	SHmedia floating point register moves (inc. fabs and fneg)
;; fparith_media SHmedia single precision floating point arithmetic
;; fpconv_media	SHmedia single precision floating point conversions
;; fstore_media	SHmedia floating point register store instructions
;; gettr_media	SHmedia gettr instruction
;; invalidate_line_media SHmedia invaldiate_line sequence
;; jump_media	SHmedia unconditional branch instructions
;; load_media	SHmedia general register load instructions
;; pt_media	SHmedia pt instruction (expanded by assembler)
;; ptabs_media	SHmedia ptabs instruction
;; store_media	SHmedia general register store instructions
;; mcmp_media	SHmedia multimedia compare, absolute, saturating ops
;; mac_media	SHmedia mac-style fixed point operations
;; d2mpy_media	SHmedia: two 32 bit integer multiplies
;; atrans	SHmedia approximate transcendential functions
;; ustore_media	SHmedia unaligned stores
;; nil		no-op move, will be deleted.

(define_attr "type"
 "mt_group,cbranch,jump,jump_ind,arith,arith3,arith3b,dyn_shift,load,load_si,fload,store,move,fmove,smpy,dmpy,return,pload,prset,pstore,prget,pcload,pcload_si,pcfload,rte,sfunc,call,fp,fdiv,ftrc_s,dfp_arith,dfp_cmp,dfp_conv,dfdiv,gp_fpul,fpul_gp,mac_gp,mem_fpscr,gp_fpscr,cwb,arith_media,cbranch_media,cmp_media,dfdiv_media,dfmul_media,dfparith_media,dfpconv_media,dmpy_media,fcmp_media,fdiv_media,fload_media,fmove_media,fparith_media,fpconv_media,fstore_media,gettr_media,invalidate_line_media,jump_media,load_media,pt_media,ptabs_media,store_media,mcmp_media,mac_media,d2mpy_media,atrans_media,ustore_media,nil,other"
  (const_string "other"))

;; We define a new attribute namely "insn_class".We use
;; this for the DFA based pipeline description.
;;
;; mt_group      SH4 "mt" group instructions.
;;
;; ex_group      SH4 "ex" group instructions.
;;
;; ls_group      SH4 "ls" group instructions.
;;

(define_attr "insn_class"
  "mt_group,ex_group,ls_group,br_group,fe_group,co_group,none"
  (cond [(eq_attr "type" "move,mt_group") (const_string "mt_group")
         (eq_attr "type" "arith,dyn_shift") (const_string "ex_group")
	 (eq_attr "type" "fmove,load,pcload,load_si,pcload_si,fload,pcfload,store,gp_fpul,fpul_gp") (const_string "ls_group")
	 (eq_attr "type" "cbranch,jump") (const_string "br_group")
	 (eq_attr "type" "fp,fdiv,ftrc_s,dfp_arith,dfp_conv,dfdiv")
	   (const_string "fe_group")
	 (eq_attr "type" "jump_ind,smpy,dmpy,mac_gp,return,pload,prset,pstore,prget,rte,sfunc,call,dfp_cmp,mem_fpscr,gp_fpscr,cwb") (const_string "co_group")]
	(const_string "none")))
;; nil are zero instructions, and arith3 / arith3b are multiple instructions,
;; so these do not belong in an insn group, although they are modeled
;; with their own define_insn_reservations.

;; Indicate what precision must be selected in fpscr for this insn, if any.

(define_attr "fp_mode" "single,double,none" (const_string "none"))

; If a conditional branch destination is within -252..258 bytes away
; from the instruction it can be 2 bytes long.  Something in the
; range -4090..4100 bytes can be 6 bytes long.  All other conditional
; branches are initially assumed to be 16 bytes long.
; In machine_dependent_reorg, we split all branches that are longer than
; 2 bytes.

;; The maximum range used for SImode constant pool entries is 1018.  A final
;; instruction can add 8 bytes while only being 4 bytes in size, thus we
;; can have a total of 1022 bytes in the pool.  Add 4 bytes for a branch
;; instruction around the pool table, 2 bytes of alignment before the table,
;; and 30 bytes of alignment after the table.  That gives a maximum total
;; pool size of 1058 bytes.
;; Worst case code/pool content size ratio is 1:2 (using asms).
;; Thus, in the worst case, there is one instruction in front of a maximum
;; sized pool, and then there are 1052 bytes of pool for every 508 bytes of
;; code.  For the last n bytes of code, there are 2n + 36 bytes of pool.
;; If we have a forward branch, the initial table will be put after the
;; unconditional branch.
;;
;; ??? We could do much better by keeping track of the actual pcloads within
;; the branch range and in the pcload range in front of the branch range.

;; ??? This looks ugly because genattrtab won't allow if_then_else or cond
;; inside an le.
(define_attr "short_cbranch_p" "no,yes"
  (cond [(ne (symbol_ref "mdep_reorg_phase <= SH_FIXUP_PCLOAD") (const_int 0))
	 (const_string "no")
	 (leu (plus (minus (match_dup 0) (pc)) (const_int 252)) (const_int 506))
	 (const_string "yes")
	 (ne (symbol_ref "NEXT_INSN (PREV_INSN (insn)) != insn") (const_int 0))
	 (const_string "no")
	 (leu (plus (minus (match_dup 0) (pc)) (const_int 252)) (const_int 508))
	 (const_string "yes")
         ] (const_string "no")))

(define_attr "med_branch_p" "no,yes"
  (cond [(leu (plus (minus (match_dup 0) (pc)) (const_int 990))
	      (const_int 1988))
	 (const_string "yes")
	 (ne (symbol_ref "mdep_reorg_phase <= SH_FIXUP_PCLOAD") (const_int 0))
	 (const_string "no")
	 (leu (plus (minus (match_dup 0) (pc)) (const_int 4092))
	      (const_int 8186))
	 (const_string "yes")
	 ] (const_string "no")))

(define_attr "med_cbranch_p" "no,yes"
  (cond [(leu (plus (minus (match_dup 0) (pc)) (const_int 988))
	      (const_int 1986))
	 (const_string "yes")
	 (ne (symbol_ref "mdep_reorg_phase <= SH_FIXUP_PCLOAD") (const_int 0))
	 (const_string "no")
	 (leu (plus (minus (match_dup 0) (pc)) (const_int 4090))
	       (const_int 8184))
	 (const_string "yes")
	 ] (const_string "no")))

(define_attr "braf_branch_p" "no,yes"
  (cond [(ne (symbol_ref "! TARGET_SH2") (const_int 0))
	 (const_string "no")
	 (leu (plus (minus (match_dup 0) (pc)) (const_int 10330))
	      (const_int 20660))
	 (const_string "yes")
	 (ne (symbol_ref "mdep_reorg_phase <= SH_FIXUP_PCLOAD") (const_int 0))
	 (const_string "no")
	 (leu (plus (minus (match_dup 0) (pc)) (const_int 32764))
	      (const_int 65530))
	 (const_string "yes")
	 ] (const_string "no")))

(define_attr "braf_cbranch_p" "no,yes"
  (cond [(ne (symbol_ref "! TARGET_SH2") (const_int 0))
	 (const_string "no")
	 (leu (plus (minus (match_dup 0) (pc)) (const_int 10328))
	      (const_int 20658))
	 (const_string "yes")
	 (ne (symbol_ref "mdep_reorg_phase <= SH_FIXUP_PCLOAD") (const_int 0))
	 (const_string "no")
	 (leu (plus (minus (match_dup 0) (pc)) (const_int 32762))
	      (const_int 65528))
	 (const_string "yes")
	 ] (const_string "no")))

; An unconditional jump in the range -4092..4098 can be 2 bytes long.
; For wider ranges, we need a combination of a code and a data part.
; If we can get a scratch register for a long range jump, the code
; part can be 4 bytes long; otherwise, it must be 8 bytes long.
; If the jump is in the range -32764..32770, the data part can be 2 bytes
; long; otherwise, it must be 6 bytes long.

; All other instructions are two bytes long by default.

;; ??? This should use something like *branch_p (minus (match_dup 0) (pc)),
;; but getattrtab doesn't understand this.
(define_attr "length" ""
  (cond [(eq_attr "type" "cbranch")
	 (cond [(eq_attr "short_cbranch_p" "yes")
		(const_int 2)
		(eq_attr "med_cbranch_p" "yes")
		(const_int 6)
		(eq_attr "braf_cbranch_p" "yes")
		(const_int 12)
;; ??? using pc is not computed transitively.
		(ne (match_dup 0) (match_dup 0))
		(const_int 14)
		(ne (symbol_ref ("flag_pic")) (const_int 0))
		(const_int 24)
		] (const_int 16))
	 (eq_attr "type" "jump")
	 (cond [(eq_attr "med_branch_p" "yes")
		(const_int 2)
		(and (eq (symbol_ref "GET_CODE (prev_nonnote_insn (insn))")
			 (symbol_ref "INSN"))