s390.md

linux下的gcc编译器

;;- Machine description for GNU compiler -- S/390 / zSeries version.
;;  Copyright (C) 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
;;  Contributed by Hartmut Penner ([e-mail]) and
;;                 Ulrich Weigand ([e-mail]).
;; This file is part of GNU CC.

;; GNU CC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 2, or (at your option)
;; any later version.

;; GNU CC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
;; GNU General Public License for more details.

;; You should have received a copy of the GNU General Public License
;; along with GNU CC; see the file COPYING.  If not, write to
;; the Free Software Foundation, 59 Temple Place - Suite 330,
;; Boston, MA 02111-1307, USA.

;;
;; Special constraints for s/390 machine description:
;;
;;    a -- Any address register from 1 to 15.
;;    d -- Any register from 0 to 15.
;;    I -- An 8-bit constant (0..255).
;;    J -- A 12-bit constant (0..4095).
;;    K -- A 16-bit constant (-32768..32767).
;;    Q -- A memory reference without index-register.
;;    S -- Valid operand for the LARL instruction.
;;
;; Special formats used for outputting 390 instructions.
;;
;;   %b -- Print a constant byte integer.               xy
;;   %h -- Print a signed 16-bit.                       wxyz
;;   %N -- Print next register (second word of a DImode reg) or next word.
;;   %M -- Print next register (second word of a TImode reg) or next word.
;;   %O -- Print the offset of a memory reference (PLUS (REG) (CONST_INT)).
;;   %R -- Print the register of a memory reference (PLUS (REG) (CONST_INT)).
;;
;; We have a special constraint for pattern matching.
;;
;;   s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
;;

;;
;; UNSPEC usage
;;

(define_constants
  [; TLS relocation specifiers
   (UNSPEC_TLSGD		500)
   (UNSPEC_TLSLDM		501)
   (UNSPEC_NTPOFF               502)
   (UNSPEC_DTPOFF               503)
   (UNSPEC_GOTNTPOFF            504)
   (UNSPEC_INDNTPOFF            505)

   ; TLS support
   (UNSPEC_TP			510)
   (UNSPEC_TLSLDM_NTPOFF	511)
   (UNSPEC_TLS_LOAD		512)
 ])

;;
;; UNSPEC_VOLATILE usage
;;

(define_constants
  [; TLS support
   (UNSPECV_SET_TP		500)
  ])


;; Define an insn type attribute.  This is used in function unit delay
;; computations.

(define_attr "type" "none,integer,load,lr,la,lm,stm,cs,vs,store,imul,lmul,fmul,idiv,ldiv,fdiv,branch,jsr,other,o2,o3"
  (const_string "integer"))

;; Insn are devide in two classes:
;;   mem: Insn accessing memory
;;   reg: Insn operands all in registers

(define_attr "atype" "reg,mem"
  (const_string "reg"))

;; Generic pipeline function unit.  

(define_function_unit "integer" 1 0
  (eq_attr "type" "none") 0 0)

(define_function_unit "integer" 1 0
  (eq_attr "type" "integer") 1 1)

(define_function_unit "integer" 1 0
  (eq_attr "type" "load") 1 1)

(define_function_unit "integer" 1 0
  (eq_attr "type" "la") 1 1)

(define_function_unit "integer" 1 0
  (eq_attr "type" "lr") 1 1)

(define_function_unit "integer" 1 0
  (eq_attr "type" "store") 1 1)

(define_function_unit "integer" 1 0
  (eq_attr "type" "lm") 2 2)

(define_function_unit "integer" 1 0
  (eq_attr "type" "stm") 2 2)

(define_function_unit "integer" 1 0
  (eq_attr "type" "cs") 5 5)

(define_function_unit "integer" 1 0
  (eq_attr "type" "vs") 30 30)

(define_function_unit "integer" 1 0
  (eq_attr "type" "jsr") 5 5)

(define_function_unit "integer" 1 0
  (eq_attr "type" "imul") 7 7)

(define_function_unit "integer" 1 0
  (eq_attr "type" "fmul") 6 6)

(define_function_unit "integer" 1 0
  (eq_attr "type" "idiv") 33 33)

(define_function_unit "integer" 1 0
  (eq_attr "type" "fdiv") 33 33)

(define_function_unit "integer" 1 0
  (eq_attr "type" "o2") 2 2)

(define_function_unit "integer" 1 0
  (eq_attr "type" "o3") 3 3)

(define_function_unit "integer" 1 0
  (eq_attr "type" "other") 5 5)

;; Operand type. Used to default length attribute values

(define_attr "op_type"
  "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE"
  (const_string "RX"))

;; Length in bytes.

(define_attr "length" ""
(cond [ (eq_attr "op_type" "E")    (const_int 2)
         (eq_attr "op_type" "RR")  (const_int 2)
         (eq_attr "op_type" "RX")  (const_int 4)
         (eq_attr "op_type" "RI")  (const_int 4)
         (eq_attr "op_type" "RRE") (const_int 4)
         (eq_attr "op_type" "RS")  (const_int 4)
         (eq_attr "op_type" "RSI") (const_int 4)
         (eq_attr "op_type" "RX")  (const_int 4)
         (eq_attr "op_type" "S")   (const_int 4)
         (eq_attr "op_type" "SI")  (const_int 4)
         (eq_attr "op_type" "SS")  (const_int 6)
         (eq_attr "op_type" "SSE") (const_int 6)
         (eq_attr "op_type" "RXE") (const_int 6)
         (eq_attr "op_type" "RSE") (const_int 6)
         (eq_attr "op_type" "RIL") (const_int 6)]
         (const_int 4)))

;; Define attributes for `asm' insns.

(define_asm_attributes [(set_attr "type" "other")
                        (set_attr "op_type" "NN")])

;;
;;  Condition Codes
;;
;
;   CCL:  Zero     Nonzero   Zero      Nonzero      (AL, ALR, SL, SLR, N, NC, NI, NR, O, OC, OI, OR, X, XC, XI, XR)
;   CCA:  Zero     <Zero     >Zero     Overflow     (A, AR, AH, AHI, S, SR, SH, SHI, LTR, LCR, LNR, LPR, SLA, SLDA, SLA, SRDA)
;   CCU:  Equal    ULess     UGreater  --           (CL, CLR, CLI, CLM)
;   CCS:  Equal    SLess     SGreater  --           (C, CR, CH, CHI, ICM)
;   CCT:  Zero     Mixed     Mixed     Ones         (TM, TMH, TML)
 
;   CCZ  -> CCL / CCZ1
;   CCZ1 -> CCA/CCU/CCS/CCT
;   CCS  -> CCA
 
;   String:    CLC, CLCL, CLCLE, CLST, CUSE, MVCL, MVCLE, MVPG, MVST, SRST
;   Clobber:   CKSM, CFC, CS, CDS, CUUTF, CUTFU, PLO, SPM, STCK, STCKE, TS, TRT, TRE, UPT


;;
;;- Compare instructions.
;;

(define_expand "cmpdi"
  [(set (reg:CC 33)
        (compare:CC (match_operand:DI 0 "register_operand" "")
                    (match_operand:DI 1 "general_operand" "")))]
  "TARGET_64BIT"
  "
{
  s390_compare_op0 = operands[0];
  s390_compare_op1 = operands[1];
  DONE;
}")

(define_expand "cmpsi"
  [(set (reg:CC 33)
        (compare:CC (match_operand:SI 0 "register_operand" "")
                    (match_operand:SI 1 "general_operand" "")))]
  ""
  "
{
  s390_compare_op0 = operands[0];
  s390_compare_op1 = operands[1];
  DONE;
}")

(define_expand "cmpdf"
  [(set (reg:CC 33)
        (compare:CC (match_operand:DF 0 "register_operand" "")
                    (match_operand:DF 1 "general_operand" "")))]
  "TARGET_HARD_FLOAT"
  "
{
  s390_compare_op0 = operands[0];
  s390_compare_op1 = operands[1];
  DONE;
}")

(define_expand "cmpsf"
  [(set (reg:CC 33)
        (compare:CC (match_operand:SF 0 "register_operand" "")
                    (match_operand:SF 1 "general_operand" "")))]
  "TARGET_HARD_FLOAT"
  "
{
  s390_compare_op0 = operands[0];
  s390_compare_op1 = operands[1];
  DONE;
}")


; Test-under-Mask (zero_extract) instructions

(define_insn "*tmdi_ext"
  [(set (reg 33)
        (compare (zero_extract:DI (match_operand:DI 0 "register_operand" "d")
	                          (match_operand:DI 1 "const_int_operand" "n")
                                  (match_operand:DI 2 "const_int_operand" "n"))
                 (const_int 0)))]
  "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT
   && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0 
   && INTVAL (operands[1]) + INTVAL (operands[2]) <= 64
   && (INTVAL (operands[1]) + INTVAL (operands[2]) - 1) >> 4
      == INTVAL (operands[2]) >> 4"
  "*
{
  int part = INTVAL (operands[2]) >> 4;
  int block = (1 << INTVAL (operands[1])) - 1;
  int shift = 16 - INTVAL (operands[1]) - (INTVAL (operands[2]) & 15);

  operands[2] = GEN_INT (block << shift);

  switch (part)
    {
      case 0: return \"tmhh\\t%0,%x2\";
      case 1: return \"tmhl\\t%0,%x2\";
      case 2: return \"tmlh\\t%0,%x2\";
      case 3: return \"tmll\\t%0,%x2\";
      default: abort ();
    }
}"
  [(set_attr "op_type" "RI")])

(define_insn "*tmsi_ext"
  [(set (reg 33)
        (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "d")
	                          (match_operand:SI 1 "const_int_operand" "n")
                                  (match_operand:SI 2 "const_int_operand" "n"))
                 (const_int 0)))]
  "s390_match_ccmode(insn, CCTmode)
   && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0 
   && INTVAL (operands[1]) + INTVAL (operands[2]) <= 32
   && (INTVAL (operands[1]) + INTVAL (operands[2]) - 1) >> 4
      == INTVAL (operands[2]) >> 4"
  "*
{
  int part = INTVAL (operands[2]) >> 4;
  int block = (1 << INTVAL (operands[1])) - 1;
  int shift = 16 - INTVAL (operands[1]) - (INTVAL (operands[2]) & 15);

  operands[2] = GEN_INT (block << shift);

  switch (part)
    {
      case 0: return \"tmh\\t%0,%x2\";
      case 1: return \"tml\\t%0,%x2\";
      default: abort ();
    }
}"
  [(set_attr "op_type" "RI")])

(define_insn "*tmqi_ext"
  [(set (reg 33)
        (compare (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q")
	                          (match_operand:SI 1 "const_int_operand" "n")
                                  (match_operand:SI 2 "const_int_operand" "n"))
                 (const_int 0)))]
  "s390_match_ccmode(insn, CCTmode)
   && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0 
   && INTVAL (operands[1]) + INTVAL (operands[2]) <= 8"
  "*
{
  int block = (1 << INTVAL (operands[1])) - 1;
  int shift = 8 - INTVAL (operands[1]) - INTVAL (operands[2]);

  operands[2] = GEN_INT (block << shift);
  return \"tm\\t%0,%b2\";
}"
  [(set_attr "op_type" "SI")
   (set_attr "atype"   "mem")])

; Test-under-Mask instructions

(define_insn "*tmdi_mem"
  [(set (reg 33)
        (compare (and:DI (match_operand:DI 0 "memory_operand" "Q")
                         (match_operand:DI 1 "immediate_operand" "n"))
                 (match_operand:DI 2 "immediate_operand" "n")))]
  "TARGET_64BIT
   && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))
   && s390_single_qi (operands[1], DImode, 0) >= 0"
  "*
{
  int part = s390_single_qi (operands[1], DImode, 0);
  operands[1] = GEN_INT (s390_extract_qi (operands[1], DImode, part));

  operands[0] = gen_rtx_MEM (QImode, 
			     plus_constant (XEXP (operands[0], 0), part));
  return \"tm\\t%0,%b1\";
}"
  [(set_attr "op_type" "SI")
   (set_attr "atype"   "mem")])

(define_insn "*tmsi_mem"
  [(set (reg 33)
        (compare (and:SI (match_operand:SI 0 "memory_operand" "Q")
                         (match_operand:SI 1 "immediate_operand" "n"))
                 (match_operand:SI 2 "immediate_operand" "n")))]
  "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))
   && s390_single_qi (operands[1], SImode, 0) >= 0"
  "*
{
  int part = s390_single_qi (operands[1], SImode, 0);
  operands[1] = GEN_INT (s390_extract_qi (operands[1], SImode, part));

  operands[0] = gen_rtx_MEM (QImode, 
			     plus_constant (XEXP (operands[0], 0), part));
  return \"tm\\t%0,%b1\";
}"
  [(set_attr "op_type" "SI")
   (set_attr "atype"   "mem")])

(define_insn "*tmhi_mem"
  [(set (reg 33)
        (compare (and:SI (subreg:SI (match_operand:HI 0 "memory_operand" "Q") 0)
                         (match_operand:SI 1 "immediate_operand" "n"))
                 (match_operand:SI 2 "immediate_operand" "n")))]
  "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))
   && s390_single_qi (operands[1], HImode, 0) >= 0"
  "*
{
  int part = s390_single_qi (operands[1], HImode, 0);
  operands[1] = GEN_INT (s390_extract_qi (operands[1], HImode, part));

  operands[0] = gen_rtx_MEM (QImode, 
			     plus_constant (XEXP (operands[0], 0), part));
  return \"tm\\t%0,%b1\";
}"
  [(set_attr "op_type" "SI")
   (set_attr "atype"   "mem")])

(define_insn "*tmqi_mem"
  [(set (reg 33)
        (compare (and:SI (subreg:SI (match_operand:QI 0 "memory_operand" "Q") 0)
                         (match_operand:SI 1 "immediate_operand" "n"))
                 (match_operand:SI 2 "immediate_operand" "n")))]
  "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))"
  "tm\\t%0,%b1"
  [(set_attr "op_type" "SI")
   (set_attr "atype"   "mem")])

(define_insn "*tmdi_reg"
  [(set (reg 33)
        (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d")
                         (match_operand:DI 1 "immediate_operand" "n"))
                 (match_operand:DI 2 "immediate_operand" "n")))]
  "TARGET_64BIT
   && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 1))
   && s390_single_hi (operands[1], DImode, 0) >= 0"
  "*
{
  int part = s390_single_hi (operands[1], DImode, 0);
  operands[1] = GEN_INT (s390_extract_hi (operands[1], DImode, part));

  switch (part)
    {
      case 0: return \"tmhh\\t%0,%x1\";
      case 1: return \"tmhl\\t%0,%x1\";
      case 2: return \"tmlh\\t%0,%x1\";
      case 3: return \"tmll\\t%0,%x1\";
      default: abort ();
    }
}"
  [(set_attr "op_type" "RI")])

(define_insn "*tmsi_reg"
  [(set (reg 33)
        (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d")
                         (match_operand:SI 1 "immediate_operand" "n"))
                 (match_operand:SI 2 "immediate_operand" "n")))]
  "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 1))
   && s390_single_hi (operands[1], SImode, 0) >= 0"
  "*
{
  int part = s390_single_hi (operands[1], SImode, 0);
  operands[1] = GEN_INT (s390_extract_hi (operands[1], SImode, part));

  switch (part)
    {
      case 0: return \"tmh\\t%0,%x1\";
      case 1: return \"tml\\t%0,%x1\";
      default: abort ();
    }
}"