📄 cd.rpt
字号:
E E E E E E I E E E E I E I E E E I E E E E E E E E I E
R R R R R R O R R R R N R N L R R O R R R R R R R R O R
V V V V V V V V V V T V T V V V V V V V V V V V
E E E E E E E E E E E E E E E E E E E E E E
D D D D D D D D D D D D D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
$ = Pin has PCI I/O option enabled. Pin is neither '5.0 V'- nor '3.3 V'-tolerant.
Device-Specific Information: d:\eda cunfang\edadianzhizuo\10k10 rom\led\cd.rpt
cd
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A1 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 3/22( 13%)
A2 8/ 8(100%) 10/ 8(125%) 7/ 8( 87%) 0/2 0/2 6/22( 27%)
A3 8/ 8(100%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 20/22( 90%)
A4 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 19/22( 86%)
A5 8/ 8(100%) 2/ 8( 25%) 0/ 8( 0%) 0/2 0/2 20/22( 90%)
A6 6/ 8( 75%) 5/ 8( 62%) 2/ 8( 25%) 0/2 0/2 8/22( 36%)
A7 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 0/2 0/2 13/22( 59%)
A8 8/ 8(100%) 3/ 8( 37%) 0/ 8( 0%) 0/2 0/2 17/22( 77%)
A9 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 0/2 0/2 18/22( 81%)
A10 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 20/22( 90%)
A11 8/ 8(100%) 2/ 8( 25%) 0/ 8( 0%) 0/2 0/2 19/22( 86%)
A12 8/ 8(100%) 3/ 8( 37%) 6/ 8( 75%) 0/2 0/2 8/22( 36%)
A13 6/ 8( 75%) 0/ 8( 0%) 6/ 8( 75%) 0/2 0/2 8/22( 36%)
A14 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
A15 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
A16 8/ 8(100%) 6/ 8( 75%) 4/ 8( 50%) 0/2 0/2 9/22( 40%)
A17 8/ 8(100%) 8/ 8(100%) 7/ 8( 87%) 1/2 1/2 4/22( 18%)
A18 7/ 8( 87%) 1/ 8( 12%) 5/ 8( 62%) 0/2 0/2 13/22( 59%)
A19 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 18/22( 81%)
A20 4/ 8( 50%) 2/ 8( 25%) 2/ 8( 25%) 0/2 0/2 6/22( 27%)
A21 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 17/22( 77%)
A22 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 19/22( 86%)
A23 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
A24 7/ 8( 87%) 0/ 8( 0%) 6/ 8( 75%) 0/2 0/2 9/22( 40%)
A25 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 12/22( 54%)
A26 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 13/22( 59%)
A28 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 18/22( 81%)
A29 8/ 8(100%) 0/ 8( 0%) 7/ 8( 87%) 0/2 0/2 8/22( 36%)
A30 2/ 8( 25%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 7/22( 31%)
A31 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 14/22( 63%)
A32 8/ 8(100%) 4/ 8( 50%) 6/ 8( 75%) 1/2 1/2 6/22( 27%)
A33 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
A34 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 12/22( 54%)
A35 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
A36 8/ 8(100%) 1/ 8( 12%) 7/ 8( 87%) 0/2 0/2 11/22( 50%)
C1 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 20/22( 90%)
C2 8/ 8(100%) 5/ 8( 62%) 4/ 8( 50%) 0/2 0/2 8/22( 36%)
C3 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 19/22( 86%)
C4 3/ 8( 37%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 10/22( 45%)
C5 8/ 8(100%) 5/ 8( 62%) 5/ 8( 62%) 0/2 0/2 9/22( 40%)
C6 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 20/22( 90%)
C7 7/ 8( 87%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 20/22( 90%)
C8 7/ 8( 87%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 18/22( 81%)
C9 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 20/22( 90%)
C10 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 20/22( 90%)
C11 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 17/22( 77%)
C12 6/ 8( 75%) 2/ 8( 25%) 5/ 8( 62%) 0/2 0/2 10/22( 45%)
C13 7/ 8( 87%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 18/22( 81%)
C14 8/ 8(100%) 1/ 8( 12%) 6/ 8( 75%) 0/2 0/2 13/22( 59%)
C15 4/ 8( 50%) 3/ 8( 37%) 2/ 8( 25%) 0/2 0/2 4/22( 18%)
C16 8/ 8(100%) 5/ 8( 62%) 4/ 8( 50%) 0/2 0/2 10/22( 45%)
C17 8/ 8(100%) 2/ 8( 25%) 6/ 8( 75%) 0/2 0/2 9/22( 40%)
C18 2/ 8( 25%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 7/22( 31%)
C19 5/ 8( 62%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 16/22( 72%)
C20 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 20/22( 90%)
C21 6/ 8( 75%) 1/ 8( 12%) 5/ 8( 62%) 0/2 0/2 7/22( 31%)
C22 5/ 8( 62%) 2/ 8( 25%) 3/ 8( 37%) 0/2 0/2 6/22( 27%)
C23 7/ 8( 87%) 0/ 8( 0%) 7/ 8( 87%) 0/2 0/2 8/22( 36%)
C24 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 14/22( 63%)
C25 7/ 8( 87%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 17/22( 77%)
C26 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 16/22( 72%)
C27 7/ 8( 87%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 17/22( 77%)
C28 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 12/22( 54%)
C29 8/ 8(100%) 3/ 8( 37%) 6/ 8( 75%) 1/2 1/2 9/22( 40%)
C30 3/ 8( 37%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 10/22( 45%)
C31 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 18/22( 81%)
C32 8/ 8(100%) 2/ 8( 25%) 1/ 8( 12%) 0/2 0/2 16/22( 72%)
C33 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
C34 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 10/22( 45%)
C35 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 20/22( 90%)
C36 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 0/2 0/2 11/22( 50%)
D1 7/ 8( 87%) 3/ 8( 37%) 6/ 8( 75%) 0/2 0/2 7/22( 31%)
D2 4/ 8( 50%) 2/ 8( 25%) 2/ 8( 25%) 0/2 0/2 5/22( 22%)
D3 8/ 8(100%) 5/ 8( 62%) 7/ 8( 87%) 0/2 0/2 8/22( 36%)
D4 6/ 8( 75%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 16/22( 72%)
D5 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 20/22( 90%)
D6 8/ 8(100%) 5/ 8( 62%) 1/ 8( 12%) 0/2 0/2 18/22( 81%)
D7 6/ 8( 75%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 9/22( 40%)
D8 8/ 8(100%) 4/ 8( 50%) 2/ 8( 25%) 0/2 0/2 13/22( 59%)
D10 5/ 8( 62%) 4/ 8( 50%) 3/ 8( 37%) 0/2 0/2 6/22( 27%)
D11 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 16/22( 72%)
D12 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 11/22( 50%)
D13 8/ 8(100%) 2/ 8( 25%) 5/ 8( 62%) 0/2 0/2 12/22( 54%)
D14 8/ 8(100%) 3/ 8( 37%) 0/ 8( 0%) 0/2 0/2 18/22( 81%)
D15 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 0/2 0/2 19/22( 86%)
D16 8/ 8(100%) 2/ 8( 25%) 1/ 8( 12%) 0/2 0/2 14/22( 63%)
D17 1/ 8( 12%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
D18 8/ 8(100%) 6/ 8( 75%) 3/ 8( 37%) 0/2 0/2 11/22( 50%)
D19 8/ 8(100%) 5/ 8( 62%) 4/ 8( 50%) 0/2 0/2 8/22( 36%)
D25 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 18/22( 81%)
D29 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 3/22( 13%)
D30 8/ 8(100%) 2/ 8( 25%) 5/ 8( 62%) 0/2 0/2 12/22( 54%)
F1 8/ 8(100%) 3/ 8( 37%) 2/ 8( 25%) 0/2 0/2 14/22( 63%)
F2 8/ 8(100%) 4/ 8( 50%) 5/ 8( 62%) 0/2 0/2 9/22( 40%)
F3 8/ 8(100%) 4/ 8( 50%) 6/ 8( 75%) 1/2 1/2 4/22( 18%)
F5 8/ 8(100%) 2/ 8( 25%) 5/ 8( 62%) 0/2 0/2 10/22( 45%)
F6 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 16/22( 72%)
F9 7/ 8( 87%) 2/ 8( 25%) 1/ 8( 12%) 0/2 0/2 17/22( 77%)
F10 8/ 8(100%) 4/ 8( 50%) 6/ 8( 75%) 0/2 0/2 7/22( 31%)
F11 8/ 8(100%) 2/ 8( 25%) 0/ 8( 0%) 0/2 0/2 18/22( 81%)
F12 1/ 8( 12%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
F13 7/ 8( 87%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 17/22( 77%)
F14 8/ 8(100%) 3/ 8( 37%) 1/ 8( 12%) 0/2 0/2 18/22( 81%)
F15 1/ 8( 12%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
F16 8/ 8(100%) 7/ 8( 87%) 2/ 8( 25%) 1/2 1/2 3/22( 13%)
F17 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 20/22( 90%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 3/6 ( 50%)
Total I/O pins used: 20/96 ( 20%)
Total logic cells used: 706/1728 ( 40%)
Total embedded cells used: 0/96 ( 0%)
Total EABs used: 0/6 ( 0%)
Average fan-in: 3.38/4 ( 84%)
Total fan-in: 2388/6912 ( 34%)
Total input pins required: 3
Total input I/O cell registers required: 0
Total output pins required: 20
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 706
Total flipflops required: 8
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 275/1728 ( 15%)
Logic Cell and Embedded Cell Counts
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