📄 cd.rpt
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Project Information d:\eda cunfang\edadianzhizuo\10k10 rom\led\cd.rpt
MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 06/01/2008 15:21:04
Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
** DEVICE SUMMARY **
Chip/ Input Output Bidir Memory Memory LCs
POF Device Pins Pins Pins Bits % Utilized LCs % Utilized
cd EP1K30TC144-3 3 20 0 0 0 % 706 40 %
User Pins: 3 20 0
Project Information d:\eda cunfang\edadianzhizuo\10k10 rom\led\cd.rpt
** PROJECT TIMING MESSAGES **
Warning: Timing characteristics of device EP1K30TC144-3 are preliminary
Project Information d:\eda cunfang\edadianzhizuo\10k10 rom\led\cd.rpt
** PIN/LOCATION/CHIP ASSIGNMENTS **
Actual
User Assignments
Assignments (if different) Node Name
cd@95 L0
cd@17 L1
cd@96 L2
cd@14 L3
cd@18 L4
cd@12 L5
cd@13 L6
cd@11 L7
cd@132 L8
cd@19 L9
cd@20 L10
cd@89 L11
cd@23 L12
cd@22 L13
cd@21 L14
cd@41 L15
Project Information d:\eda cunfang\edadianzhizuo\10k10 rom\led\cd.rpt
** FILE HIERARCHY **
|and2:31|
|and2:31|lpm_add_sub:69|
|and2:31|lpm_add_sub:69|addcore:adder|
|and2:31|lpm_add_sub:69|altshift:result_ext_latency_ffs|
|and2:31|lpm_add_sub:69|altshift:carry_ext_latency_ffs|
|and2:31|lpm_add_sub:69|altshift:oflow_ext_latency_ffs|
|rom:36|
|and1:37|
|and1:37|lpm_add_sub:69|
|and1:37|lpm_add_sub:69|addcore:adder|
|and1:37|lpm_add_sub:69|altshift:result_ext_latency_ffs|
|and1:37|lpm_add_sub:69|altshift:carry_ext_latency_ffs|
|and1:37|lpm_add_sub:69|altshift:oflow_ext_latency_ffs|
Device-Specific Information: d:\eda cunfang\edadianzhizuo\10k10 rom\led\cd.rpt
cd
***** Logic for device 'cd' compiled without errors.
Device: EP1K30TC144-3
ACEX 1K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
MultiVolt I/O = OFF
R R R R R R R R R R R R R R R R R R R R R R R R R R
E E E E E E E E E E E E E E E E E E E E E E E E E E
S S S S S S S S S S S S S V S S S S S S S S S S S S S
E E E E E E E E E V E E E E C C E E E E E E E V E E E E E E
R R R R R R R R R C R R R R C K R R R R R R R C R R R R R R
V V V V V G V V V V C V V V G V I G D G G V V V V V V V C V V V V V V
E E E E E N E E E E I E L E E N E N N S N N E E E E E E E I E E E E E E
D D D D D D D D D D O D 8 D D D D T D P D D D D D D D D D O D D D D D D
--------------------------------------------------------------------------_
/ 144 142 140 138 136 134 132 130 128 126 124 122 120 118 116 114 112 110 |_
/ 143 141 139 137 135 133 131 129 127 125 123 121 119 117 115 113 111 109 |
#TCK | 1 108 | ^DATA0
^CONF_DONE | 2 107 | ^DCLK
^nCEO | 3 106 | ^nCE
#TDO | 4 105 | #TDI
VCCIO | 5 104 | GND
GND | 6 103 | VCCINT
AD3 | 7 102 | AD2
RESERVED | 8 101 | AD0
RESERVED | 9 100 | AD1
RESERVED | 10 99 | RESERVED
L7 | 11 98 | RESERVED
L5 | 12 97 | RESERVED
L6 | 13 96 | L2
L3 | 14 95 | L0
GND | 15 94 | VCCIO
VCCINT | 16 93 | GND
L1 | 17 92 | RESERVED
L4 | 18 91 | RESERVED
L9 | 19 EP1K30TC144-3 90 | RESERVED
L10 | 20 89 | L11
L14 | 21 88 | RESERVED
L13 | 22 87 | RESERVED
L12 | 23 86 | RESERVED
VCCIO | 24 85 | VCCINT
GND | 25 84 | GND
RESERVED | 26 83 | RESERVED
RESERVED | 27 82 | RESERVED
RESERVED | 28 81 | RESERVED
RESERVED | 29 80 | RESERVED
RESERVED | 30 79 | RESERVED
RESERVED | 31 78 | RESERVED
RESERVED | 32 77 | ^MSEL0
RESERVED | 33 76 | ^MSEL1
#TMS | 34 75 | VCCINT
^nSTATUS | 35 74 | ^nCONFIG
RESERVED | 36 73 | RESERVED
| 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 _|
\ 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 |
\---------------------------------------------------------------------------
R R R G L R R R V R R R R V R G V C H G G G R R V R R R R G R R R R V R
E E E N 1 E E E C E E E E C E N C R Z N N N E E C E E E E N E E E E C E
S S S D 5 S S S C S S S S C S D C S D D D S S C S S S S D S S S S C S
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