📄 led.rpt
字号:
_X003 = EXP( _LC082 & !_LC102 & !sel2);
_X004 = EXP(!_LC087 & !_LC102 & sel1);
_X005 = EXP( _LC084 & !_LC102 & !sel0);
_X006 = EXP(!_LC084 & !_LC102 & sel0);
_EQ018 = _X002 & _X003 & _X004 & _X005 & _X006;
_X002 = EXP(!_LC082 & !_LC102 & sel2);
_X003 = EXP( _LC082 & !_LC102 & !sel2);
_X004 = EXP(!_LC087 & !_LC102 & sel1);
_X005 = EXP( _LC084 & !_LC102 & !sel0);
_X006 = EXP(!_LC084 & !_LC102 & sel0);
-- Node name is '|ROM:1|~845~1'
-- Equation name is '_LC088', type is buried
-- synthesized logic cell
_LC088 = LCELL( _EQ019 $ _EQ020);
_EQ019 = _LC081 & !sel0 & sel1 & !sel2 & _X001 & _X002 & _X003 &
_X004 & _X005 & _X006 & _X007
# sel0 & sel1 & sel2 & _X001 & _X002 & _X003 & _X004 & _X005 &
_X006 & _X007
# !_LC081 & !sel1 & !sel2 & _X001 & _X002 & _X003 & _X004 &
_X005 & _X006 & _X007
# !_LC081 & !sel0 & !sel1 & _X001 & _X002 & _X003 & _X004 &
_X005 & _X006 & _X007;
_X001 = EXP(!_LC081 & !_LC082 & !_LC084 & !_LC087 & !sel0 & !sel1 & !sel2);
_X002 = EXP(!_LC082 & !_LC102 & sel2);
_X003 = EXP( _LC082 & !_LC102 & !sel2);
_X004 = EXP(!_LC087 & !_LC102 & sel1);
_X005 = EXP( _LC084 & !_LC102 & !sel0);
_X006 = EXP(!_LC084 & !_LC102 & sel0);
_X007 = EXP( _LC087 & !_LC102 & !sel1);
_EQ020 = _X002 & _X003 & _X004 & _X005 & _X006 & _X007;
_X002 = EXP(!_LC082 & !_LC102 & sel2);
_X003 = EXP( _LC082 & !_LC102 & !sel2);
_X004 = EXP(!_LC087 & !_LC102 & sel1);
_X005 = EXP( _LC084 & !_LC102 & !sel0);
_X006 = EXP(!_LC084 & !_LC102 & sel0);
_X007 = EXP( _LC087 & !_LC102 & !sel1);
-- Node name is '|ROM:1|~896~1'
-- Equation name is '_LC089', type is buried
-- synthesized logic cell
_LC089 = LCELL( _EQ021 $ _EQ022);
_EQ021 = sel0 & !sel1 & !sel2 & _X001 & _X003 & _X004 & _X005 & _X010 &
_X011
# !_LC082 & sel2 & _X001 & _X003 & _X004 & _X005 & _X010 &
_X011
# _LC087 & !sel1 & _X001 & _X003 & _X004 & _X005 & _X010 &
_X011
# !_LC084 & sel0 & _X001 & _X003 & _X004 & _X005 & _X010 &
_X011;
_X001 = EXP(!_LC081 & !_LC082 & !_LC084 & !_LC087 & !sel0 & !sel1 & !sel2);
_X003 = EXP( _LC082 & !_LC102 & !sel2);
_X004 = EXP(!_LC087 & !_LC102 & sel1);
_X005 = EXP( _LC084 & !_LC102 & !sel0);
_X010 = EXP(!_LC081 & !_LC102 & sel0);
_X011 = EXP(!_LC081 & !_LC102 & !sel1);
_EQ022 = _X003 & _X004 & _X005 & _X010 & _X011;
_X003 = EXP( _LC082 & !_LC102 & !sel2);
_X004 = EXP(!_LC087 & !_LC102 & sel1);
_X005 = EXP( _LC084 & !_LC102 & !sel0);
_X010 = EXP(!_LC081 & !_LC102 & sel0);
_X011 = EXP(!_LC081 & !_LC102 & !sel1);
-- Node name is '|ROM:1|~947~1'
-- Equation name is '_LC090', type is buried
-- synthesized logic cell
_LC090 = LCELL( _EQ023 $ _EQ024);
_EQ023 = _LC081 & sel0 & !sel1 & sel2 & _X001 & _X002 & _X005 &
_X006 & _X007 & _X012
# !_LC081 & sel0 & sel1 & _X001 & _X002 & _X005 & _X006 &
_X007 & _X012
# _LC082 & !sel2 & _X001 & _X002 & _X005 & _X006 & _X007 &
_X012
# !_LC087 & sel1 & _X001 & _X002 & _X005 & _X006 & _X007 &
_X012;
_X001 = EXP(!_LC081 & !_LC082 & !_LC084 & !_LC087 & !sel0 & !sel1 & !sel2);
_X002 = EXP(!_LC082 & !_LC102 & sel2);
_X005 = EXP( _LC084 & !_LC102 & !sel0);
_X006 = EXP(!_LC084 & !_LC102 & sel0);
_X007 = EXP( _LC087 & !_LC102 & !sel1);
_X012 = EXP(!_LC081 & !_LC102 & !sel2);
_EQ024 = _X002 & _X005 & _X006 & _X007 & _X012;
_X002 = EXP(!_LC082 & !_LC102 & sel2);
_X005 = EXP( _LC084 & !_LC102 & !sel0);
_X006 = EXP(!_LC084 & !_LC102 & sel0);
_X007 = EXP( _LC087 & !_LC102 & !sel1);
_X012 = EXP(!_LC081 & !_LC102 & !sel2);
-- Node name is '|ROM:1|~995~1'
-- Equation name is '_LC065', type is buried
-- synthesized logic cell
_LC065 = LCELL( _EQ025 $ !_LC091);
_EQ025 = !_LC081 & !_LC091 & sel0 & sel1 & sel2
# _LC081 & !_LC091 & !sel0 & !sel1 & sel2
# !_LC081 & !_LC091 & !sel1 & !sel2
# !_LC082 & !_LC091 & sel2;
-- Node name is '|ROM:1|~995~2'
-- Equation name is '_LC091', type is buried
-- synthesized logic cell
_LC091 = LCELL( _EQ026 $ GND);
_EQ026 = _LC087 & !sel1
# !_LC084 & sel0
# _LC082 & !sel2
# !_LC087 & sel1
# _LC084 & !sel0;
-- Node name is '|ROM:1|~1017~1'
-- Equation name is '_LC097', type is buried
-- synthesized logic cell
_LC097 = LCELL( _EQ027 $ _EQ028);
_EQ027 = CLR & _LC081 & !_LC099 & sel0 & !sel1 & sel2 & _X001 & _X013 &
_X014 & _X015 & _X016
# CLR & _LC081 & !_LC099 & sel0 & sel1 & !sel2 & _X001 & _X013 &
_X014 & _X015 & _X016
# CLR & !_LC081 & !_LC099 & !sel1 & !sel2 & _X001 & _X013 &
_X014 & _X015 & _X016
# CLR & !_LC081 & !_LC099 & !sel0 & !sel1 & _X001 & _X013 &
_X014 & _X015 & _X016;
_X001 = EXP(!_LC081 & !_LC082 & !_LC084 & !_LC087 & !sel0 & !sel1 & !sel2);
_X013 = EXP(!CLR & !_LC097);
_X014 = EXP( CLR & !_LC082 & !_LC102 & sel2);
_X015 = EXP( CLR & _LC087 & !_LC102 & !sel1);
_X016 = EXP( CLR & !_LC084 & !_LC102 & sel0);
_EQ028 = !_LC099 & _X013 & _X014 & _X015 & _X016;
_X013 = EXP(!CLR & !_LC097);
_X014 = EXP( CLR & !_LC082 & !_LC102 & sel2);
_X015 = EXP( CLR & _LC087 & !_LC102 & !sel1);
_X016 = EXP( CLR & !_LC084 & !_LC102 & sel0);
-- Node name is '|ROM:1|~1017~2'
-- Equation name is '_LC099', type is buried
-- synthesized logic cell
_LC099 = LCELL( _EQ029 $ GND);
_EQ029 = CLR & _LC082 & !_LC102 & !sel2
# CLR & !_LC087 & !_LC102 & sel1
# CLR & _LC084 & !_LC102 & !sel0;
-- Node name is '|ROM:1|~1023~1'
-- Equation name is '_LC113', type is buried
-- synthesized logic cell
_LC113 = LCELL( _EQ030 $ GND);
_EQ030 = CLR & _LC100
# !CLR & _LC113
# _LC100 & _LC113;
-- Node name is '|ROM:1|~1029~1'
-- Equation name is '_LC103', type is buried
-- synthesized logic cell
_LC103 = LCELL( _EQ031 $ GND);
_EQ031 = CLR & _LC096
# !CLR & _LC103
# _LC096 & _LC103;
-- Node name is '|ROM:1|~1035~1'
-- Equation name is '_LC112', type is buried
-- synthesized logic cell
_LC112 = LCELL( _EQ032 $ _EQ033);
_EQ032 = CLR & _LC081 & !_LC099 & !sel0 & sel1 & !sel2 & _X001 & _X014 &
_X015 & _X016 & _X017
# CLR & !_LC099 & sel0 & sel1 & sel2 & _X001 & _X014 & _X015 &
_X016 & _X017
# CLR & !_LC081 & !_LC099 & !sel1 & !sel2 & _X001 & _X014 &
_X015 & _X016 & _X017
# CLR & !_LC081 & !_LC099 & !sel0 & !sel1 & _X001 & _X014 &
_X015 & _X016 & _X017;
_X001 = EXP(!_LC081 & !_LC082 & !_LC084 & !_LC087 & !sel0 & !sel1 & !sel2);
_X014 = EXP( CLR & !_LC082 & !_LC102 & sel2);
_X015 = EXP( CLR & _LC087 & !_LC102 & !sel1);
_X016 = EXP( CLR & !_LC084 & !_LC102 & sel0);
_X017 = EXP(!CLR & !_LC112);
_EQ033 = !_LC099 & _X014 & _X015 & _X016 & _X017;
_X014 = EXP( CLR & !_LC082 & !_LC102 & sel2);
_X015 = EXP( CLR & _LC087 & !_LC102 & !sel1);
_X016 = EXP( CLR & !_LC084 & !_LC102 & sel0);
_X017 = EXP(!CLR & !_LC112);
-- Node name is '|ROM:1|~1041~1'
-- Equation name is '_LC111', type is buried
-- synthesized logic cell
_LC111 = LCELL( _EQ034 $ _EQ035);
_EQ034 = CLR & !_LC099 & sel0 & !sel1 & !sel2 & _X001 & _X018 & _X019 &
_X020
# CLR & !_LC082 & !_LC099 & sel2 & _X001 & _X018 & _X019 &
_X020
# CLR & _LC087 & !_LC099 & !sel1 & _X001 & _X018 & _X019 &
_X020
# CLR & !_LC084 & !_LC099 & sel0 & _X001 & _X018 & _X019 &
_X020;
_X001 = EXP(!_LC081 & !_LC082 & !_LC084 & !_LC087 & !sel0 & !sel1 & !sel2);
_X018 = EXP( CLR & !_LC081 & !_LC102 & sel0);
_X019 = EXP( CLR & !_LC081 & !_LC102 & !sel1);
_X020 = EXP(!CLR & !_LC111);
_EQ035 = !_LC099 & _X018 & _X019 & _X020;
_X018 = EXP( CLR & !_LC081 & !_LC102 & sel0);
_X019 = EXP( CLR & !_LC081 & !_LC102 & !sel1);
_X020 = EXP(!CLR & !_LC111);
-- Node name is '|ROM:1|~1047~1'
-- Equation name is '_LC110', type is buried
-- synthesized logic cell
_LC110 = LCELL( _EQ036 $ GND);
_EQ036 = CLR & _LC090
# !CLR & _LC110
# _LC090 & _LC110;
-- Node name is '|ROM:1|~1053~1'
-- Equation name is '_LC108', type is buried
-- synthesized logic cell
_LC108 = LCELL( _EQ037 $ VCC);
_EQ037 = CLR & !_LC081 & !_LC082 & !_LC084 & !_LC087 & !sel0 & !sel1 &
!sel2
# CLR & !_LC065
# !CLR & !_LC108
# !_LC081 & !_LC082 & !_LC084 & !_LC087 & !_LC108 & !sel0 & !sel1 &
!sel2
# !_LC065 & !_LC108;
-- Shareable expanders that are duplicated in multiple LABs:
-- _X001 occurs in LABs F, G
Project Information f:\test36\led.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 4,197K
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -