📄 led.rpt
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Device-Specific Information: f:\test36\led.rpt
led
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'E':
Logic cells placed in LAB 'E'
+- LC65 |ROM:1|~995~1
|
| Other LABs fed by signals
| that feed LAB 'E'
LC | | A B C D E F G H | Logic cells that feed LAB 'E':
Pin
83 -> - | - - - - - - - - | <-- CLK0
2 -> - | - - - - - - - - | <-- CLK1
1 -> - | - - - - - - * * | <-- CLR
LC81 -> * | - - - - * * * - | <-- |AND2:3|dou3
LC82 -> * | - - - - * * * - | <-- |AND2:3|dou2
LC91 -> * | - - - - * - - - | <-- |ROM:1|~995~2
LC86 -> * | - - - - * * * - | <-- sel0
LC85 -> * | - - - - * * * - | <-- sel1
LC83 -> * | - - - - * * * - | <-- sel2
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: f:\test36\led.rpt
led
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'F':
Logic cells placed in LAB 'F'
+------------------------- LC81 |AND2:3|dou3
| +----------------------- LC82 |AND2:3|dou2
| | +--------------------- LC87 |AND2:3|dou1
| | | +------------------- LC84 |AND2:3|dou0
| | | | +----------------- LC92 |ROM:1|~692~1
| | | | | +--------------- LC96 |ROM:1|~794~1
| | | | | | +------------- LC88 |ROM:1|~845~1
| | | | | | | +----------- LC89 |ROM:1|~896~1
| | | | | | | | +--------- LC90 |ROM:1|~947~1
| | | | | | | | | +------- LC91 |ROM:1|~995~2
| | | | | | | | | | +----- LC86 sel0
| | | | | | | | | | | +--- LC85 sel1
| | | | | | | | | | | | +- LC83 sel2
| | | | | | | | | | | | |
| | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | that feed LAB 'F'
LC | | | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'F':
LC81 -> * - - - * * * * * - - - - | - - - - * * * - | <-- |AND2:3|dou3
LC82 -> * * - - * * * * * * - - - | - - - - * * * - | <-- |AND2:3|dou2
LC87 -> * * * - * * * * * * - - - | - - - - - * * - | <-- |AND2:3|dou1
LC84 -> * * * * * * * * * * - - - | - - - - - * * - | <-- |AND2:3|dou0
LC86 -> - - - - * * * * * * * * * | - - - - * * * - | <-- sel0
LC85 -> - - - - * * * * * * - * * | - - - - * * * - | <-- sel1
LC83 -> - - - - * * * * * * - - * | - - - - * * * - | <-- sel2
Pin
83 -> - - - - - - - - - - - - - | - - - - - - - - | <-- CLK0
2 -> - - - - - - - - - - - - - | - - - - - - - - | <-- CLK1
1 -> - - - - - - - - - - - - - | - - - - - - * * | <-- CLR
LC106-> * - - - - - - - - - - - - | - - - - - * - - | <-- |AND2:3|LPM_ADD_SUB:69|addcore:adder|addcore:adder0|result_node3
LC102-> - - - - * * * * * - - - - | - - - - - * * - | <-- |ROM:1|~689~1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: f:\test36\led.rpt
led
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'G':
Logic cells placed in LAB 'G'
+------------------------------- LC106 |AND2:3|LPM_ADD_SUB:69|addcore:adder|addcore:adder0|result_node3
| +----------------------------- LC109 C
| | +--------------------------- LC107 D
| | | +------------------------- LC105 E
| | | | +----------------------- LC104 F
| | | | | +--------------------- LC101 G
| | | | | | +------------------- LC102 |ROM:1|~689~1
| | | | | | | +----------------- LC100 |ROM:1|~743~1
| | | | | | | | +--------------- LC98 |ROM:1|~743~2
| | | | | | | | | +------------- LC97 |ROM:1|~1017~1
| | | | | | | | | | +----------- LC99 |ROM:1|~1017~2
| | | | | | | | | | | +--------- LC103 |ROM:1|~1029~1
| | | | | | | | | | | | +------- LC112 |ROM:1|~1035~1
| | | | | | | | | | | | | +----- LC111 |ROM:1|~1041~1
| | | | | | | | | | | | | | +--- LC110 |ROM:1|~1047~1
| | | | | | | | | | | | | | | +- LC108 |ROM:1|~1053~1
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'G'
LC | | | | | | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'G':
LC102-> - - - - - - - - - * * - * * - - | - - - - - * * - | <-- |ROM:1|~689~1
LC98 -> - - - - - - - * - - - - - - - - | - - - - - - * - | <-- |ROM:1|~743~2
LC97 -> - - - - - - - - - * - - - - - - | - - - - - - * * | <-- |ROM:1|~1017~1
LC99 -> - - - - - - - - - * - - * * - - | - - - - - - * - | <-- |ROM:1|~1017~2
LC103-> - * - - - - - - - - - * - - - - | - - - - - - * - | <-- |ROM:1|~1029~1
LC112-> - - * - - - - - - - - - * - - - | - - - - - - * - | <-- |ROM:1|~1035~1
LC111-> - - - * - - - - - - - - - * - - | - - - - - - * - | <-- |ROM:1|~1041~1
LC110-> - - - - * - - - - - - - - - * - | - - - - - - * - | <-- |ROM:1|~1047~1
LC108-> - - - - - * - - - - - - - - - * | - - - - - - * - | <-- |ROM:1|~1053~1
Pin
83 -> - - - - - - - - - - - - - - - - | - - - - - - - - | <-- CLK0
2 -> - - - - - - - - - - - - - - - - | - - - - - - - - | <-- CLK1
1 -> - * * * * * - - - * * * * * * * | - - - - - - * * | <-- CLR
LC81 -> * - - - - * * * * * - - * * - * | - - - - * * * - | <-- |AND2:3|dou3
LC82 -> * - - - - * * * * * * - * * - * | - - - - * * * - | <-- |AND2:3|dou2
LC87 -> * - - - - * * * * * * - * * - * | - - - - - * * - | <-- |AND2:3|dou1
LC84 -> * - - - - * * * * * * - * * - * | - - - - - * * - | <-- |AND2:3|dou0
LC96 -> - * - - - - - - - - - * - - - - | - - - - - - * - | <-- |ROM:1|~794~1
LC88 -> - - * - - - - - - - - - - - - - | - - - - - - * - | <-- |ROM:1|~845~1
LC89 -> - - - * - - - - - - - - - - - - | - - - - - - * - | <-- |ROM:1|~896~1
LC90 -> - - - - * - - - - - - - - - * - | - - - - - - * - | <-- |ROM:1|~947~1
LC65 -> - - - - - * - - - - - - - - - * | - - - - - - * - | <-- |ROM:1|~995~1
LC86 -> - - - - - * * * * * * - * * - * | - - - - * * * - | <-- sel0
LC85 -> - - - - - * * * * * * - * * - * | - - - - * * * - | <-- sel1
LC83 -> - - - - - * * * * * * - * * - * | - - - - * * * - | <-- sel2
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: f:\test36\led.rpt
led
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'H':
Logic cells placed in LAB 'H'
+----- LC117 A
| +--- LC115 B
| | +- LC113 |ROM:1|~1023~1
| | |
| | | Other LABs fed by signals
| | | that feed LAB 'H'
LC | | | | A B C D E F G H | Logic cells that feed LAB 'H':
LC113-> - * * | - - - - - - - * | <-- |ROM:1|~1023~1
Pin
83 -> - - - | - - - - - - - - | <-- CLK0
2 -> - - - | - - - - - - - - | <-- CLK1
1 -> * * * | - - - - - - * * | <-- CLR
LC92 -> * - - | - - - - - - - * | <-- |ROM:1|~692~1
LC100-> - * * | - - - - - - - * | <-- |ROM:1|~743~1
LC97 -> * - - | - - - - - - * * | <-- |ROM:1|~1017~1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: f:\test36\led.rpt
led
** EQUATIONS **
CLK0 : INPUT;
CLK1 : INPUT;
CLR : INPUT;
-- Node name is 'A'
-- Equation name is 'A', location is LC117, type is output.
A = LCELL( _EQ001 $ GND);
_EQ001 = CLR & _LC092
# !CLR & _LC097;
-- Node name is 'B'
-- Equation name is 'B', location is LC115, type is output.
B = LCELL( _EQ002 $ GND);
_EQ002 = CLR & _LC100
# !CLR & _LC113;
-- Node name is 'C'
-- Equation name is 'C', location is LC109, type is output.
C = LCELL( _EQ003 $ GND);
_EQ003 = CLR & _LC096
# !CLR & _LC103;
-- Node name is 'D'
-- Equation name is 'D', location is LC107, type is output.
D = LCELL( _EQ004 $ GND);
_EQ004 = CLR & _LC088
# !CLR & _LC112;
-- Node name is 'E'
-- Equation name is 'E', location is LC105, type is output.
E = LCELL( _EQ005 $ GND);
_EQ005 = CLR & _LC089
# !CLR & _LC111;
-- Node name is 'F'
-- Equation name is 'F', location is LC104, type is output.
F = LCELL( _EQ006 $ GND);
_EQ006 = CLR & _LC090
# !CLR & _LC110;
-- Node name is 'G'
-- Equation name is 'G', location is LC101, type is output.
G = LCELL( _EQ007 $ GND);
_EQ007 = CLR & _LC065 & _X001
# !CLR & _LC108;
_X001 = EXP(!_LC081 & !_LC082 & !_LC084 & !_LC087 & !sel0 & !sel1 & !sel2);
-- Node name is 'sel0' = '|AND1:2|dou0'
-- Equation name is 'sel0', type is output
sel0 = TFFE( VCC, GLOBAL( CLK0), GLOBAL( CLR), VCC, VCC);
-- Node name is 'sel1' = '|AND1:2|dou1'
-- Equation name is 'sel1', type is output
sel1 = TFFE( sel0, GLOBAL( CLK0), GLOBAL( CLR), VCC, VCC);
-- Node name is 'sel2' = '|AND1:2|dou2'
-- Equation name is 'sel2', type is output
sel2 = TFFE( _EQ008, GLOBAL( CLK0), GLOBAL( CLR), VCC, VCC);
_EQ008 = sel0 & sel1;
-- Node name is '|AND2:3|:10' = '|AND2:3|dou0'
-- Equation name is '_LC084', type is buried
_LC084 = TFFE( VCC, GLOBAL( CLK1), GLOBAL( CLR), VCC, VCC);
-- Node name is '|AND2:3|:9' = '|AND2:3|dou1'
-- Equation name is '_LC087', type is buried
_LC087 = TFFE( _LC084, GLOBAL( CLK1), GLOBAL( CLR), VCC, VCC);
-- Node name is '|AND2:3|:8' = '|AND2:3|dou2'
-- Equation name is '_LC082', type is buried
_LC082 = TFFE( _EQ009, GLOBAL( CLK1), GLOBAL( CLR), VCC, VCC);
_EQ009 = _LC084 & _LC087;
-- Node name is '|AND2:3|:7' = '|AND2:3|dou3'
-- Equation name is '_LC081', type is buried
_LC081 = DFFE( _EQ010 $ _LC106, GLOBAL( CLK1), GLOBAL( CLR), VCC, VCC);
_EQ010 = _LC081 & _LC082 & _LC084 & _LC087 & _LC106;
-- Node name is '|AND2:3|LPM_ADD_SUB:69|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC106', type is buried
_LC106 = LCELL( _LC081 $ _EQ011);
_EQ011 = _LC082 & _LC084 & _LC087;
-- Node name is '|ROM:1|~689~1'
-- Equation name is '_LC102', type is buried
-- synthesized logic cell
_LC102 = LCELL( _EQ012 $ GND);
_EQ012 = !_LC081 & !_LC082 & !_LC084 & !_LC087 & !sel0 & !sel1 & !sel2;
-- Node name is '|ROM:1|~692~1'
-- Equation name is '_LC092', type is buried
-- synthesized logic cell
_LC092 = LCELL( _EQ013 $ _EQ014);
_EQ013 = _LC081 & sel0 & !sel1 & sel2 & _X001 & _X002 & _X003 &
_X004 & _X005 & _X006 & _X007
# _LC081 & sel0 & sel1 & !sel2 & _X001 & _X002 & _X003 &
_X004 & _X005 & _X006 & _X007
# !_LC081 & !sel1 & !sel2 & _X001 & _X002 & _X003 & _X004 &
_X005 & _X006 & _X007
# !_LC081 & !sel0 & !sel1 & _X001 & _X002 & _X003 & _X004 &
_X005 & _X006 & _X007;
_X001 = EXP(!_LC081 & !_LC082 & !_LC084 & !_LC087 & !sel0 & !sel1 & !sel2);
_X002 = EXP(!_LC082 & !_LC102 & sel2);
_X003 = EXP( _LC082 & !_LC102 & !sel2);
_X004 = EXP(!_LC087 & !_LC102 & sel1);
_X005 = EXP( _LC084 & !_LC102 & !sel0);
_X006 = EXP(!_LC084 & !_LC102 & sel0);
_X007 = EXP( _LC087 & !_LC102 & !sel1);
_EQ014 = _X002 & _X003 & _X004 & _X005 & _X006 & _X007;
_X002 = EXP(!_LC082 & !_LC102 & sel2);
_X003 = EXP( _LC082 & !_LC102 & !sel2);
_X004 = EXP(!_LC087 & !_LC102 & sel1);
_X005 = EXP( _LC084 & !_LC102 & !sel0);
_X006 = EXP(!_LC084 & !_LC102 & sel0);
_X007 = EXP( _LC087 & !_LC102 & !sel1);
-- Node name is '|ROM:1|~743~1'
-- Equation name is '_LC100', type is buried
-- synthesized logic cell
_LC100 = LCELL( _EQ015 $ VCC);
_EQ015 = !_LC098 & _X001 & _X008 & _X009;
_X001 = EXP(!_LC081 & !_LC082 & !_LC084 & !_LC087 & !sel0 & !sel1 & !sel2);
_X008 = EXP(!_LC082 & !_LC084 & _LC087 & !sel0 & sel1 & !sel2);
_X009 = EXP(!_LC082 & _LC084 & !_LC087 & sel0 & !sel1 & !sel2);
-- Node name is '|ROM:1|~743~2'
-- Equation name is '_LC098', type is buried
-- synthesized logic cell
_LC098 = LCELL( _EQ016 $ GND);
_EQ016 = !_LC081 & _LC082 & _LC084 & _LC087 & sel0 & sel1 & sel2
# _LC081 & _LC082 & _LC084 & !_LC087 & sel0 & !sel1 & sel2
# !_LC081 & !_LC082 & _LC084 & _LC087 & sel0 & sel1 & !sel2
# !_LC081 & _LC082 & !_LC084 & !_LC087 & !sel0 & !sel1 & sel2
# _LC081 & !_LC082 & !_LC084 & !_LC087 & !sel0 & !sel1 & !sel2;
-- Node name is '|ROM:1|~794~1'
-- Equation name is '_LC096', type is buried
-- synthesized logic cell
_LC096 = LCELL( _EQ017 $ _EQ018);
_EQ017 = _LC081 & _LC082 & _LC087 & _X001 & _X002 & _X003 & _X004 &
_X005 & _X006
# _LC081 & _LC082 & !_LC084 & _X001 & _X002 & _X003 & _X004 &
_X005 & _X006
# !_LC081 & !_LC082 & !_LC084 & _X001 & _X002 & _X003 & _X004 &
_X005 & _X006
# _LC087 & !sel1 & _X001 & _X002 & _X003 & _X004 & _X005 &
_X006;
_X001 = EXP(!_LC081 & !_LC082 & !_LC084 & !_LC087 & !sel0 & !sel1 & !sel2);
_X002 = EXP(!_LC082 & !_LC102 & sel2);
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