rom.vhd

数字钟的设计,实现正点报时的系统!.......

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ROM is port   
(CR,A6,A5,A4,A3,A2,A1,A0:  in std_logic;   
 L6,L5,L4,L3,L2,L1,L0: out std_logic);
end;
architecture arc_ROM of ROM is
signal din:  std_logic_vector(6 downto 0);
signal dout:  std_logic_vector(6 downto 0);
begin
   din<=A6&A5&A4&A3&A2&A1&A0;
process(din)     
begin          
if(CR='1')then 
case din is
 when"0000000"=>dout<="1111110"; --1    
 when"0010001"=>dout<="0110000"; --2    
 when"0100010"=>dout<="1101101"; --3    
 when"0110011"=>dout<="1111001"; --4    
 when"1000100"=>dout<="0110011"; --5    
 when"1010101"=>dout<="1011011"; --6    
 when"1100110"=>dout<="1011111"; --7    
 when"1110111"=>dout<="1110000"; --8  
 when"0001000"=>dout<="1111111"; --1    
 when"0011001"=>dout<="1111011"; --2    
 when"0101010"=>dout<="1110111"; --3    
 when"0111011"=>dout<="0011111"; --4    
 when"1001100"=>dout<="1001110"; --5    
 when"1011101"=>dout<="0111101"; --6    
 when"1101110"=>dout<="1001111"; --7    
 when"1111111"=>dout<="1000111"; --8 
 when others=>dout<="0000000";
             end case;          
        end if;
end process;
L6<=dout(6);
L5<=dout(5);
L4<=dout(4);
L3<=dout(3);
L2<=dout(2);
L1<=dout(1);
L0<=dout(0);
end arc_ROM;