📄 adsp-edn-dual-core-extended_cdef.h

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#define bfin_read_DMA1_2_CURR_ADDR()   bfin_readPTR(DMA1_2_CURR_ADDR)#define bfin_write_DMA1_2_CURR_ADDR(val) bfin_writePTR(DMA1_2_CURR_ADDR, val)#define pDMA1_2_CURR_X_COUNT           ((uint16_t volatile *)DMA1_2_CURR_X_COUNT)#define bfin_read_DMA1_2_CURR_X_COUNT() bfin_read16(DMA1_2_CURR_X_COUNT)#define bfin_write_DMA1_2_CURR_X_COUNT(val) bfin_write16(DMA1_2_CURR_X_COUNT, val)#define pDMA1_2_CURR_Y_COUNT           ((uint16_t volatile *)DMA1_2_CURR_Y_COUNT)#define bfin_read_DMA1_2_CURR_Y_COUNT() bfin_read16(DMA1_2_CURR_Y_COUNT)#define bfin_write_DMA1_2_CURR_Y_COUNT(val) bfin_write16(DMA1_2_CURR_Y_COUNT, val)#define pDMA1_2_IRQ_STATUS             ((uint16_t volatile *)DMA1_2_IRQ_STATUS)#define bfin_read_DMA1_2_IRQ_STATUS()  bfin_read16(DMA1_2_IRQ_STATUS)#define bfin_write_DMA1_2_IRQ_STATUS(val) bfin_write16(DMA1_2_IRQ_STATUS, val)#define pDMA1_2_PERIPHERAL_MAP         ((uint16_t volatile *)DMA1_2_PERIPHERAL_MAP)#define bfin_read_DMA1_2_PERIPHERAL_MAP() bfin_read16(DMA1_2_PERIPHERAL_MAP)#define bfin_write_DMA1_2_PERIPHERAL_MAP(val) bfin_write16(DMA1_2_PERIPHERAL_MAP, val)#define pDMA1_3_CONFIG                 ((uint16_t volatile *)DMA1_3_CONFIG)#define bfin_read_DMA1_3_CONFIG()      bfin_read16(DMA1_3_CONFIG)#define bfin_write_DMA1_3_CONFIG(val)  bfin_write16(DMA1_3_CONFIG, val)#define pDMA1_3_NEXT_DESC_PTR          ((void * volatile *)DMA1_3_NEXT_DESC_PTR)#define bfin_read_DMA1_3_NEXT_DESC_PTR() bfin_readPTR(DMA1_3_NEXT_DESC_PTR)#define bfin_write_DMA1_3_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_3_NEXT_DESC_PTR, val)#define pDMA1_3_START_ADDR             ((void * volatile *)DMA1_3_START_ADDR)#define bfin_read_DMA1_3_START_ADDR()  bfin_readPTR(DMA1_3_START_ADDR)#define bfin_write_DMA1_3_START_ADDR(val) bfin_writePTR(DMA1_3_START_ADDR, val)#define pDMA1_3_X_COUNT                ((uint16_t volatile *)DMA1_3_X_COUNT)#define bfin_read_DMA1_3_X_COUNT()     bfin_read16(DMA1_3_X_COUNT)#define bfin_write_DMA1_3_X_COUNT(val) bfin_write16(DMA1_3_X_COUNT, val)#define pDMA1_3_Y_COUNT                ((uint16_t volatile *)DMA1_3_Y_COUNT)#define bfin_read_DMA1_3_Y_COUNT()     bfin_read16(DMA1_3_Y_COUNT)#define bfin_write_DMA1_3_Y_COUNT(val) bfin_write16(DMA1_3_Y_COUNT, val)#define pDMA1_3_X_MODIFY               ((uint16_t volatile *)DMA1_3_X_MODIFY)#define bfin_read_DMA1_3_X_MODIFY()    bfin_read16(DMA1_3_X_MODIFY)#define bfin_write_DMA1_3_X_MODIFY(val) bfin_write16(DMA1_3_X_MODIFY, val)#define pDMA1_3_Y_MODIFY               ((uint16_t volatile *)DMA1_3_Y_MODIFY)#define bfin_read_DMA1_3_Y_MODIFY()    bfin_read16(DMA1_3_Y_MODIFY)#define bfin_write_DMA1_3_Y_MODIFY(val) bfin_write16(DMA1_3_Y_MODIFY, val)#define pDMA1_3_CURR_DESC_PTR          ((void * volatile *)DMA1_3_CURR_DESC_PTR)#define bfin_read_DMA1_3_CURR_DESC_PTR() bfin_readPTR(DMA1_3_CURR_DESC_PTR)#define bfin_write_DMA1_3_CURR_DESC_PTR(val) bfin_writePTR(DMA1_3_CURR_DESC_PTR, val)#define pDMA1_3_CURR_ADDR              ((void * volatile *)DMA1_3_CURR_ADDR)#define bfin_read_DMA1_3_CURR_ADDR()   bfin_readPTR(DMA1_3_CURR_ADDR)#define bfin_write_DMA1_3_CURR_ADDR(val) bfin_writePTR(DMA1_3_CURR_ADDR, val)#define pDMA1_3_CURR_X_COUNT           ((uint16_t volatile *)DMA1_3_CURR_X_COUNT)#define bfin_read_DMA1_3_CURR_X_COUNT() bfin_read16(DMA1_3_CURR_X_COUNT)#define bfin_write_DMA1_3_CURR_X_COUNT(val) bfin_write16(DMA1_3_CURR_X_COUNT, val)#define pDMA1_3_CURR_Y_COUNT           ((uint16_t volatile *)DMA1_3_CURR_Y_COUNT)#define bfin_read_DMA1_3_CURR_Y_COUNT() bfin_read16(DMA1_3_CURR_Y_COUNT)#define bfin_write_DMA1_3_CURR_Y_COUNT(val) bfin_write16(DMA1_3_CURR_Y_COUNT, val)#define pDMA1_3_IRQ_STATUS             ((uint16_t volatile *)DMA1_3_IRQ_STATUS)#define bfin_read_DMA1_3_IRQ_STATUS()  bfin_read16(DMA1_3_IRQ_STATUS)#define bfin_write_DMA1_3_IRQ_STATUS(val) bfin_write16(DMA1_3_IRQ_STATUS, val)#define pDMA1_3_PERIPHERAL_MAP         ((uint16_t volatile *)DMA1_3_PERIPHERAL_MAP)#define bfin_read_DMA1_3_PERIPHERAL_MAP() bfin_read16(DMA1_3_PERIPHERAL_MAP)#define bfin_write_DMA1_3_PERIPHERAL_MAP(val) bfin_write16(DMA1_3_PERIPHERAL_MAP, val)#define pDMA1_4_CONFIG                 ((uint16_t volatile *)DMA1_4_CONFIG)#define bfin_read_DMA1_4_CONFIG()      bfin_read16(DMA1_4_CONFIG)#define bfin_write_DMA1_4_CONFIG(val)  bfin_write16(DMA1_4_CONFIG, val)#define pDMA1_4_NEXT_DESC_PTR          ((void * volatile *)DMA1_4_NEXT_DESC_PTR)#define bfin_read_DMA1_4_NEXT_DESC_PTR() bfin_readPTR(DMA1_4_NEXT_DESC_PTR)#define bfin_write_DMA1_4_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_4_NEXT_DESC_PTR, val)#define pDMA1_4_START_ADDR             ((void * volatile *)DMA1_4_START_ADDR)#define bfin_read_DMA1_4_START_ADDR()  bfin_readPTR(DMA1_4_START_ADDR)#define bfin_write_DMA1_4_START_ADDR(val) bfin_writePTR(DMA1_4_START_ADDR, val)#define pDMA1_4_X_COUNT                ((uint16_t volatile *)DMA1_4_X_COUNT)#define bfin_read_DMA1_4_X_COUNT()     bfin_read16(DMA1_4_X_COUNT)#define bfin_write_DMA1_4_X_COUNT(val) bfin_write16(DMA1_4_X_COUNT, val)#define pDMA1_4_Y_COUNT                ((uint16_t volatile *)DMA1_4_Y_COUNT)#define bfin_read_DMA1_4_Y_COUNT()     bfin_read16(DMA1_4_Y_COUNT)#define bfin_write_DMA1_4_Y_COUNT(val) bfin_write16(DMA1_4_Y_COUNT, val)#define pDMA1_4_X_MODIFY               ((uint16_t volatile *)DMA1_4_X_MODIFY)#define bfin_read_DMA1_4_X_MODIFY()    bfin_read16(DMA1_4_X_MODIFY)#define bfin_write_DMA1_4_X_MODIFY(val) bfin_write16(DMA1_4_X_MODIFY, val)#define pDMA1_4_Y_MODIFY               ((uint16_t volatile *)DMA1_4_Y_MODIFY)#define bfin_read_DMA1_4_Y_MODIFY()    bfin_read16(DMA1_4_Y_MODIFY)#define bfin_write_DMA1_4_Y_MODIFY(val) bfin_write16(DMA1_4_Y_MODIFY, val)#define pDMA1_4_CURR_DESC_PTR          ((void * volatile *)DMA1_4_CURR_DESC_PTR)#define bfin_read_DMA1_4_CURR_DESC_PTR() bfin_readPTR(DMA1_4_CURR_DESC_PTR)#define bfin_write_DMA1_4_CURR_DESC_PTR(val) bfin_writePTR(DMA1_4_CURR_DESC_PTR, val)#define pDMA1_4_CURR_ADDR              ((void * volatile *)DMA1_4_CURR_ADDR)#define bfin_read_DMA1_4_CURR_ADDR()   bfin_readPTR(DMA1_4_CURR_ADDR)#define bfin_write_DMA1_4_CURR_ADDR(val) bfin_writePTR(DMA1_4_CURR_ADDR, val)#define pDMA1_4_CURR_X_COUNT           ((uint16_t volatile *)DMA1_4_CURR_X_COUNT)#define bfin_read_DMA1_4_CURR_X_COUNT() bfin_read16(DMA1_4_CURR_X_COUNT)#define bfin_write_DMA1_4_CURR_X_COUNT(val) bfin_write16(DMA1_4_CURR_X_COUNT, val)#define pDMA1_4_CURR_Y_COUNT           ((uint16_t volatile *)DMA1_4_CURR_Y_COUNT)#define bfin_read_DMA1_4_CURR_Y_COUNT() bfin_read16(DMA1_4_CURR_Y_COUNT)#define bfin_write_DMA1_4_CURR_Y_COUNT(val) bfin_write16(DMA1_4_CURR_Y_COUNT, val)#define pDMA1_4_IRQ_STATUS             ((uint16_t volatile *)DMA1_4_IRQ_STATUS)#define bfin_read_DMA1_4_IRQ_STATUS()  bfin_read16(DMA1_4_IRQ_STATUS)#define bfin_write_DMA1_4_IRQ_STATUS(val) bfin_write16(DMA1_4_IRQ_STATUS, val)#define pDMA1_4_PERIPHERAL_MAP         ((uint16_t volatile *)DMA1_4_PERIPHERAL_MAP)#define bfin_read_DMA1_4_PERIPHERAL_MAP() bfin_read16(DMA1_4_PERIPHERAL_MAP)#define bfin_write_DMA1_4_PERIPHERAL_MAP(val) bfin_write16(DMA1_4_PERIPHERAL_MAP, val)#define pDMA1_5_CONFIG                 ((uint16_t volatile *)DMA1_5_CONFIG)#define bfin_read_DMA1_5_CONFIG()      bfin_read16(DMA1_5_CONFIG)#define bfin_write_DMA1_5_CONFIG(val)  bfin_write16(DMA1_5_CONFIG, val)#define pDMA1_5_NEXT_DESC_PTR          ((void * volatile *)DMA1_5_NEXT_DESC_PTR)#define bfin_read_DMA1_5_NEXT_DESC_PTR() bfin_readPTR(DMA1_5_NEXT_DESC_PTR)#define bfin_write_DMA1_5_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_5_NEXT_DESC_PTR, val)#define pDMA1_5_START_ADDR             ((void * volatile *)DMA1_5_START_ADDR)#define bfin_read_DMA1_5_START_ADDR()  bfin_readPTR(DMA1_5_START_ADDR)#define bfin_write_DMA1_5_START_ADDR(val) bfin_writePTR(DMA1_5_START_ADDR, val)#define pDMA1_5_X_COUNT                ((uint16_t volatile *)DMA1_5_X_COUNT)#define bfin_read_DMA1_5_X_COUNT()     bfin_read16(DMA1_5_X_COUNT)#define bfin_write_DMA1_5_X_COUNT(val) bfin_write16(DMA1_5_X_COUNT, val)#define pDMA1_5_Y_COUNT                ((uint16_t volatile *)DMA1_5_Y_COUNT)#define bfin_read_DMA1_5_Y_COUNT()     bfin_read16(DMA1_5_Y_COUNT)#define bfin_write_DMA1_5_Y_COUNT(val) bfin_write16(DMA1_5_Y_COUNT, val)#define pDMA1_5_X_MODIFY               ((uint16_t volatile *)DMA1_5_X_MODIFY)#define bfin_read_DMA1_5_X_MODIFY()    bfin_read16(DMA1_5_X_MODIFY)#define bfin_write_DMA1_5_X_MODIFY(val) bfin_write16(DMA1_5_X_MODIFY, val)#define pDMA1_5_Y_MODIFY               ((uint16_t volatile *)DMA1_5_Y_MODIFY)#define bfin_read_DMA1_5_Y_MODIFY()    bfin_read16(DMA1_5_Y_MODIFY)#define bfin_write_DMA1_5_Y_MODIFY(val) bfin_write16(DMA1_5_Y_MODIFY, val)#define pDMA1_5_CURR_DESC_PTR          ((void * volatile *)DMA1_5_CURR_DESC_PTR)#define bfin_read_DMA1_5_CURR_DESC_PTR() bfin_readPTR(DMA1_5_CURR_DESC_PTR)#define bfin_write_DMA1_5_CURR_DESC_PTR(val) bfin_writePTR(DMA1_5_CURR_DESC_PTR, val)#define pDMA1_5_CURR_ADDR              ((void * volatile *)DMA1_5_CURR_ADDR)#define bfin_read_DMA1_5_CURR_ADDR()   bfin_readPTR(DMA1_5_CURR_ADDR)#define bfin_write_DMA1_5_CURR_ADDR(val) bfin_writePTR(DMA1_5_CURR_ADDR, val)#define pDMA1_5_CURR_X_COUNT           ((uint16_t volatile *)DMA1_5_CURR_X_COUNT)#define bfin_read_DMA1_5_CURR_X_COUNT() bfin_read16(DMA1_5_CURR_X_COUNT)#define bfin_write_DMA1_5_CURR_X_COUNT(val) bfin_write16(DMA1_5_CURR_X_COUNT, val)#define pDMA1_5_CURR_Y_COUNT           ((uint16_t volatile *)DMA1_5_CURR_Y_COUNT)#define bfin_read_DMA1_5_CURR_Y_COUNT() bfin_read16(DMA1_5_CURR_Y_COUNT)#define bfin_write_DMA1_5_CURR_Y_COUNT(val) bfin_write16(DMA1_5_CURR_Y_COUNT, val)#define pDMA1_5_IRQ_STATUS             ((uint16_t volatile *)DMA1_5_IRQ_STATUS)#define bfin_read_DMA1_5_IRQ_STATUS()  bfin_read16(DMA1_5_IRQ_STATUS)#define bfin_write_DMA1_5_IRQ_STATUS(val) bfin_write16(DMA1_5_IRQ_STATUS, val)#define pDMA1_5_PERIPHERAL_MAP         ((uint16_t volatile *)DMA1_5_PERIPHERAL_MAP)#define bfin_read_DMA1_5_PERIPHERAL_MAP() bfin_read16(DMA1_5_PERIPHERAL_MAP)#define bfin_write_DMA1_5_PERIPHERAL_MAP(val) bfin_write16(DMA1_5_PERIPHERAL_MAP, val)#define pDMA1_6_CONFIG                 ((uint16_t volatile *)DMA1_6_CONFIG)#define bfin_read_DMA1_6_CONFIG()      bfin_read16(DMA1_6_CONFIG)#define bfin_write_DMA1_6_CONFIG(val)  bfin_write16(DMA1_6_CONFIG, val)#define pDMA1_6_NEXT_DESC_PTR          ((void * volatile *)DMA1_6_NEXT_DESC_PTR)#define bfin_read_DMA1_6_NEXT_DESC_PTR() bfin_readPTR(DMA1_6_NEXT_DESC_PTR)#define bfin_write_DMA1_6_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_6_NEXT_DESC_PTR, val)#define pDMA1_6_START_ADDR             ((void * volatile *)DMA1_6_START_ADDR)#define bfin_read_DMA1_6_START_ADDR()  bfin_readPTR(DMA1_6_START_ADDR)#define bfin_write_DMA1_6_START_ADDR(val) bfin_writePTR(DMA1_6_START_ADDR, val)#define pDMA1_6_X_COUNT                ((uint16_t volatile *)DMA1_6_X_COUNT)#define bfin_read_DMA1_6_X_COUNT()     bfin_read16(DMA1_6_X_COUNT)#define bfin_write_DMA1_6_X_COUNT(val) bfin_write16(DMA1_6_X_COUNT, val)#define pDMA1_6_Y_COUNT                ((uint16_t volatile *)DMA1_6_Y_COUNT)#define bfin_read_DMA1_6_Y_COUNT()     bfin_read16(DMA1_6_Y_COUNT)#define bfin_write_DMA1_6_Y_COUNT(val) bfin_write16(DMA1_6_Y_COUNT, val)#define pDMA1_6_X_MODIFY               ((uint16_t volatile *)DMA1_6_X_MODIFY)#define bfin_read_DMA1_6_X_MODIFY()    bfin_read16(DMA1_6_X_MODIFY)#define bfin_write_DMA1_6_X_MODIFY(val) bfin_write16(DMA1_6_X_MODIFY, val)#define pDMA1_6_Y_MODIFY               ((uint16_t volatile *)DMA1_6_Y_MODIFY)#define bfin_read_DMA1_6_Y_MODIFY()    bfin_read16(DMA1_6_Y_MODIFY)#define bfin_write_DMA1_6_Y_MODIFY(val) bfin_write16(DMA1_6_Y_MODIFY, val)#define pDMA1_6_CURR_DESC_PTR          ((void * volatile *)DMA1_6_CURR_DESC_PTR)#define bfin_read_DMA1_6_CURR_DESC_PTR() bfin_readPTR(DMA1_6_CURR_DESC_PTR)#define bfin_write_DMA1_6_CURR_DESC_PTR(val) bfin_writePTR(DMA1_6_CURR_DESC_PTR, val)#define pDMA1_6_CURR_ADDR              ((void * volatile *)DMA1_6_CURR_ADDR)#define bfin_read_DMA1_6_CURR_ADDR()   bfin_readPTR(DMA1_6_CURR_ADDR)#define bfin_write_DMA1_6_CURR_ADDR(val) bfin_writePTR(DMA1_6_CURR_ADDR, val)#define pDMA1_6_CURR_X_COUNT           ((uint16_t volatile *)DMA1_6_CURR_X_COUNT)#define bfin_read_DMA1_6_CURR_X_COUNT() bfin_read16(DMA1_6_CURR_X_COUNT)#define bfin_write_DMA1_6_CURR_X_COUNT(val) bfin_write16(DMA1_6_CURR_X_COUNT, val)#define pDMA1_6_CURR_Y_COUNT           ((uint16_t volatile *)DMA1_6_CURR_Y_COUNT)#define bfin_read_DMA1_6_CURR_Y_COUNT() bfin_read16(DMA1_6_CURR_Y_COUNT)#define bfin_write_DMA1_6_CURR_Y_COUNT(val) bfin_write16(DMA1_6_CURR_Y_COUNT, val)#define pDMA1_6_IRQ_STATUS             ((uint16_t volatile *)DMA1_6_IRQ_STATUS)#define bfin_read_DMA1_6_IRQ_STATUS()  bfin_read16(DMA1_6_IRQ_STATUS)#define bfin_write_DMA1_6_IRQ_STATUS(val) bfin_write16(DMA1_6_IRQ_STATUS, val)#define pDMA1_6_PERIPHERAL_MAP         ((uint16_t volatile *)DMA1_6_PERIPHERAL_MAP)#define bfin_read_DMA1_6_PERIPHERAL_MAP() bfin_read16(DMA1_6_PERIPHERAL_MAP)#define bfin_write_DMA1_6_PERIPHERAL_MAP(val) bfin_write16(DMA1_6_PERIPHERAL_MAP, val)#define pDMA1_7_CONFIG                 ((uint16_t volatile *)DMA1_7_CONFIG)#define bfin_read_DMA1_7_CONFIG()      bfin_read16(DMA1_7_CONFIG)#define bfin_write_DMA1_7_CONFIG(val)  bfin_write16(DMA1_7_CONFIG, val)#define pDMA1_7_NEXT_DESC_PTR          ((void * volatile *)DMA1_7_NEXT_DESC_PTR)
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