📄 adsp-edn-dual-core-extended_cdef.h

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/* DO NOT EDIT THIS FILE * Automatically generated by generate-cdef-headers.xsl * DO NOT EDIT THIS FILE */#ifndef __BFIN_CDEF_ADSP_EDN_DUAL_CORE_extended__#define __BFIN_CDEF_ADSP_EDN_DUAL_CORE_extended__#define pPLL_CTL                       ((uint16_t volatile *)PLL_CTL)#define bfin_read_PLL_CTL()            bfin_read16(PLL_CTL)#define bfin_write_PLL_CTL(val)        bfin_write16(PLL_CTL, val)#define pPLL_DIV                       ((uint16_t volatile *)PLL_DIV)#define bfin_read_PLL_DIV()            bfin_read16(PLL_DIV)#define bfin_write_PLL_DIV(val)        bfin_write16(PLL_DIV, val)#define pVR_CTL                        ((uint16_t volatile *)VR_CTL)#define bfin_read_VR_CTL()             bfin_read16(VR_CTL)#define bfin_write_VR_CTL(val)         bfin_write16(VR_CTL, val)#define pPLL_STAT                      ((uint16_t volatile *)PLL_STAT)#define bfin_read_PLL_STAT()           bfin_read16(PLL_STAT)#define bfin_write_PLL_STAT(val)       bfin_write16(PLL_STAT, val)#define pPLL_LOCKCNT                   ((uint16_t volatile *)PLL_LOCKCNT)#define bfin_read_PLL_LOCKCNT()        bfin_read16(PLL_LOCKCNT)#define bfin_write_PLL_LOCKCNT(val)    bfin_write16(PLL_LOCKCNT, val)#define pCHIPID                        ((uint32_t volatile *)CHIPID)#define bfin_read_CHIPID()             bfin_read32(CHIPID)#define bfin_write_CHIPID(val)         bfin_write32(CHIPID, val)#define pSPI_CTL                       ((uint16_t volatile *)SPI_CTL)#define bfin_read_SPI_CTL()            bfin_read16(SPI_CTL)#define bfin_write_SPI_CTL(val)        bfin_write16(SPI_CTL, val)#define pSPI_FLG                       ((uint16_t volatile *)SPI_FLG)#define bfin_read_SPI_FLG()            bfin_read16(SPI_FLG)#define bfin_write_SPI_FLG(val)        bfin_write16(SPI_FLG, val)#define pSPI_STAT                      ((uint16_t volatile *)SPI_STAT)#define bfin_read_SPI_STAT()           bfin_read16(SPI_STAT)#define bfin_write_SPI_STAT(val)       bfin_write16(SPI_STAT, val)#define pSPI_TDBR                      ((uint16_t volatile *)SPI_TDBR)#define bfin_read_SPI_TDBR()           bfin_read16(SPI_TDBR)#define bfin_write_SPI_TDBR(val)       bfin_write16(SPI_TDBR, val)#define pSPI_RDBR                      ((uint16_t volatile *)SPI_RDBR)#define bfin_read_SPI_RDBR()           bfin_read16(SPI_RDBR)#define bfin_write_SPI_RDBR(val)       bfin_write16(SPI_RDBR, val)#define pSPI_BAUD                      ((uint16_t volatile *)SPI_BAUD)#define bfin_read_SPI_BAUD()           bfin_read16(SPI_BAUD)#define bfin_write_SPI_BAUD(val)       bfin_write16(SPI_BAUD, val)#define pSPI_SHADOW                    ((uint16_t volatile *)SPI_SHADOW)#define bfin_read_SPI_SHADOW()         bfin_read16(SPI_SHADOW)#define bfin_write_SPI_SHADOW(val)     bfin_write16(SPI_SHADOW, val)#define pWDOGA_CTL                     ((uint16_t volatile *)WDOGA_CTL)#define bfin_read_WDOGA_CTL()          bfin_read16(WDOGA_CTL)#define bfin_write_WDOGA_CTL(val)      bfin_write16(WDOGA_CTL, val)#define pWDOGA_CNT                     ((uint32_t volatile *)WDOGA_CNT)#define bfin_read_WDOGA_CNT()          bfin_read32(WDOGA_CNT)#define bfin_write_WDOGA_CNT(val)      bfin_write32(WDOGA_CNT, val)#define pWDOGA_STAT                    ((uint32_t volatile *)WDOGA_STAT)#define bfin_read_WDOGA_STAT()         bfin_read32(WDOGA_STAT)#define bfin_write_WDOGA_STAT(val)     bfin_write32(WDOGA_STAT, val)#define pWDOGB_CTL                     ((uint16_t volatile *)WDOGB_CTL)#define bfin_read_WDOGB_CTL()          bfin_read16(WDOGB_CTL)#define bfin_write_WDOGB_CTL(val)      bfin_write16(WDOGB_CTL, val)#define pWDOGB_CNT                     ((uint32_t volatile *)WDOGB_CNT)#define bfin_read_WDOGB_CNT()          bfin_read32(WDOGB_CNT)#define bfin_write_WDOGB_CNT(val)      bfin_write32(WDOGB_CNT, val)#define pWDOGB_STAT                    ((uint32_t volatile *)WDOGB_STAT)#define bfin_read_WDOGB_STAT()         bfin_read32(WDOGB_STAT)#define bfin_write_WDOGB_STAT(val)     bfin_write32(WDOGB_STAT, val)#define pDMA1_TC_PER                   ((uint16_t volatile *)DMA1_TC_PER) /* Traffic Control Periods */#define bfin_read_DMA1_TC_PER()        bfin_read16(DMA1_TC_PER)#define bfin_write_DMA1_TC_PER(val)    bfin_write16(DMA1_TC_PER, val)#define pDMA1_TC_CNT                   ((uint16_t volatile *)DMA1_TC_CNT) /* Traffic Control Current Counts */#define bfin_read_DMA1_TC_CNT()        bfin_read16(DMA1_TC_CNT)#define bfin_write_DMA1_TC_CNT(val)    bfin_write16(DMA1_TC_CNT, val)#define pDMA1_0_CONFIG                 ((uint16_t volatile *)DMA1_0_CONFIG)#define bfin_read_DMA1_0_CONFIG()      bfin_read16(DMA1_0_CONFIG)#define bfin_write_DMA1_0_CONFIG(val)  bfin_write16(DMA1_0_CONFIG, val)#define pDMA1_0_NEXT_DESC_PTR          ((void * volatile *)DMA1_0_NEXT_DESC_PTR)#define bfin_read_DMA1_0_NEXT_DESC_PTR() bfin_readPTR(DMA1_0_NEXT_DESC_PTR)#define bfin_write_DMA1_0_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_0_NEXT_DESC_PTR, val)#define pDMA1_0_START_ADDR             ((void * volatile *)DMA1_0_START_ADDR)#define bfin_read_DMA1_0_START_ADDR()  bfin_readPTR(DMA1_0_START_ADDR)#define bfin_write_DMA1_0_START_ADDR(val) bfin_writePTR(DMA1_0_START_ADDR, val)#define pDMA1_0_X_COUNT                ((uint16_t volatile *)DMA1_0_X_COUNT)#define bfin_read_DMA1_0_X_COUNT()     bfin_read16(DMA1_0_X_COUNT)#define bfin_write_DMA1_0_X_COUNT(val) bfin_write16(DMA1_0_X_COUNT, val)#define pDMA1_0_Y_COUNT                ((uint16_t volatile *)DMA1_0_Y_COUNT)#define bfin_read_DMA1_0_Y_COUNT()     bfin_read16(DMA1_0_Y_COUNT)#define bfin_write_DMA1_0_Y_COUNT(val) bfin_write16(DMA1_0_Y_COUNT, val)#define pDMA1_0_X_MODIFY               ((uint16_t volatile *)DMA1_0_X_MODIFY)#define bfin_read_DMA1_0_X_MODIFY()    bfin_read16(DMA1_0_X_MODIFY)#define bfin_write_DMA1_0_X_MODIFY(val) bfin_write16(DMA1_0_X_MODIFY, val)#define pDMA1_0_Y_MODIFY               ((uint16_t volatile *)DMA1_0_Y_MODIFY)#define bfin_read_DMA1_0_Y_MODIFY()    bfin_read16(DMA1_0_Y_MODIFY)#define bfin_write_DMA1_0_Y_MODIFY(val) bfin_write16(DMA1_0_Y_MODIFY, val)#define pDMA1_0_CURR_DESC_PTR          ((void * volatile *)DMA1_0_CURR_DESC_PTR)#define bfin_read_DMA1_0_CURR_DESC_PTR() bfin_readPTR(DMA1_0_CURR_DESC_PTR)#define bfin_write_DMA1_0_CURR_DESC_PTR(val) bfin_writePTR(DMA1_0_CURR_DESC_PTR, val)#define pDMA1_0_CURR_ADDR              ((void * volatile *)DMA1_0_CURR_ADDR)#define bfin_read_DMA1_0_CURR_ADDR()   bfin_readPTR(DMA1_0_CURR_ADDR)#define bfin_write_DMA1_0_CURR_ADDR(val) bfin_writePTR(DMA1_0_CURR_ADDR, val)#define pDMA1_0_CURR_X_COUNT           ((uint16_t volatile *)DMA1_0_CURR_X_COUNT)#define bfin_read_DMA1_0_CURR_X_COUNT() bfin_read16(DMA1_0_CURR_X_COUNT)#define bfin_write_DMA1_0_CURR_X_COUNT(val) bfin_write16(DMA1_0_CURR_X_COUNT, val)#define pDMA1_0_CURR_Y_COUNT           ((uint16_t volatile *)DMA1_0_CURR_Y_COUNT)#define bfin_read_DMA1_0_CURR_Y_COUNT() bfin_read16(DMA1_0_CURR_Y_COUNT)#define bfin_write_DMA1_0_CURR_Y_COUNT(val) bfin_write16(DMA1_0_CURR_Y_COUNT, val)#define pDMA1_0_IRQ_STATUS             ((uint16_t volatile *)DMA1_0_IRQ_STATUS)#define bfin_read_DMA1_0_IRQ_STATUS()  bfin_read16(DMA1_0_IRQ_STATUS)#define bfin_write_DMA1_0_IRQ_STATUS(val) bfin_write16(DMA1_0_IRQ_STATUS, val)#define pDMA1_0_PERIPHERAL_MAP         ((uint16_t volatile *)DMA1_0_PERIPHERAL_MAP)#define bfin_read_DMA1_0_PERIPHERAL_MAP() bfin_read16(DMA1_0_PERIPHERAL_MAP)#define bfin_write_DMA1_0_PERIPHERAL_MAP(val) bfin_write16(DMA1_0_PERIPHERAL_MAP, val)#define pDMA1_1_CONFIG                 ((uint16_t volatile *)DMA1_1_CONFIG)#define bfin_read_DMA1_1_CONFIG()      bfin_read16(DMA1_1_CONFIG)#define bfin_write_DMA1_1_CONFIG(val)  bfin_write16(DMA1_1_CONFIG, val)#define pDMA1_1_NEXT_DESC_PTR          ((void * volatile *)DMA1_1_NEXT_DESC_PTR)#define bfin_read_DMA1_1_NEXT_DESC_PTR() bfin_readPTR(DMA1_1_NEXT_DESC_PTR)#define bfin_write_DMA1_1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_1_NEXT_DESC_PTR, val)#define pDMA1_1_START_ADDR             ((void * volatile *)DMA1_1_START_ADDR)#define bfin_read_DMA1_1_START_ADDR()  bfin_readPTR(DMA1_1_START_ADDR)#define bfin_write_DMA1_1_START_ADDR(val) bfin_writePTR(DMA1_1_START_ADDR, val)#define pDMA1_1_X_COUNT                ((uint16_t volatile *)DMA1_1_X_COUNT)#define bfin_read_DMA1_1_X_COUNT()     bfin_read16(DMA1_1_X_COUNT)#define bfin_write_DMA1_1_X_COUNT(val) bfin_write16(DMA1_1_X_COUNT, val)#define pDMA1_1_Y_COUNT                ((uint16_t volatile *)DMA1_1_Y_COUNT)#define bfin_read_DMA1_1_Y_COUNT()     bfin_read16(DMA1_1_Y_COUNT)#define bfin_write_DMA1_1_Y_COUNT(val) bfin_write16(DMA1_1_Y_COUNT, val)#define pDMA1_1_X_MODIFY               ((uint16_t volatile *)DMA1_1_X_MODIFY)#define bfin_read_DMA1_1_X_MODIFY()    bfin_read16(DMA1_1_X_MODIFY)#define bfin_write_DMA1_1_X_MODIFY(val) bfin_write16(DMA1_1_X_MODIFY, val)#define pDMA1_1_Y_MODIFY               ((uint16_t volatile *)DMA1_1_Y_MODIFY)#define bfin_read_DMA1_1_Y_MODIFY()    bfin_read16(DMA1_1_Y_MODIFY)#define bfin_write_DMA1_1_Y_MODIFY(val) bfin_write16(DMA1_1_Y_MODIFY, val)#define pDMA1_1_CURR_DESC_PTR          ((void * volatile *)DMA1_1_CURR_DESC_PTR)#define bfin_read_DMA1_1_CURR_DESC_PTR() bfin_readPTR(DMA1_1_CURR_DESC_PTR)#define bfin_write_DMA1_1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_1_CURR_DESC_PTR, val)#define pDMA1_1_CURR_ADDR              ((void * volatile *)DMA1_1_CURR_ADDR)#define bfin_read_DMA1_1_CURR_ADDR()   bfin_readPTR(DMA1_1_CURR_ADDR)#define bfin_write_DMA1_1_CURR_ADDR(val) bfin_writePTR(DMA1_1_CURR_ADDR, val)#define pDMA1_1_CURR_X_COUNT           ((uint16_t volatile *)DMA1_1_CURR_X_COUNT)#define bfin_read_DMA1_1_CURR_X_COUNT() bfin_read16(DMA1_1_CURR_X_COUNT)#define bfin_write_DMA1_1_CURR_X_COUNT(val) bfin_write16(DMA1_1_CURR_X_COUNT, val)#define pDMA1_1_CURR_Y_COUNT           ((uint16_t volatile *)DMA1_1_CURR_Y_COUNT)#define bfin_read_DMA1_1_CURR_Y_COUNT() bfin_read16(DMA1_1_CURR_Y_COUNT)#define bfin_write_DMA1_1_CURR_Y_COUNT(val) bfin_write16(DMA1_1_CURR_Y_COUNT, val)#define pDMA1_1_IRQ_STATUS             ((uint16_t volatile *)DMA1_1_IRQ_STATUS)#define bfin_read_DMA1_1_IRQ_STATUS()  bfin_read16(DMA1_1_IRQ_STATUS)#define bfin_write_DMA1_1_IRQ_STATUS(val) bfin_write16(DMA1_1_IRQ_STATUS, val)#define pDMA1_1_PERIPHERAL_MAP         ((uint16_t volatile *)DMA1_1_PERIPHERAL_MAP)#define bfin_read_DMA1_1_PERIPHERAL_MAP() bfin_read16(DMA1_1_PERIPHERAL_MAP)#define bfin_write_DMA1_1_PERIPHERAL_MAP(val) bfin_write16(DMA1_1_PERIPHERAL_MAP, val)#define pDMA1_2_CONFIG                 ((uint16_t volatile *)DMA1_2_CONFIG)#define bfin_read_DMA1_2_CONFIG()      bfin_read16(DMA1_2_CONFIG)#define bfin_write_DMA1_2_CONFIG(val)  bfin_write16(DMA1_2_CONFIG, val)#define pDMA1_2_NEXT_DESC_PTR          ((void * volatile *)DMA1_2_NEXT_DESC_PTR)#define bfin_read_DMA1_2_NEXT_DESC_PTR() bfin_readPTR(DMA1_2_NEXT_DESC_PTR)#define bfin_write_DMA1_2_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_2_NEXT_DESC_PTR, val)#define pDMA1_2_START_ADDR             ((void * volatile *)DMA1_2_START_ADDR)#define bfin_read_DMA1_2_START_ADDR()  bfin_readPTR(DMA1_2_START_ADDR)#define bfin_write_DMA1_2_START_ADDR(val) bfin_writePTR(DMA1_2_START_ADDR, val)#define pDMA1_2_X_COUNT                ((uint16_t volatile *)DMA1_2_X_COUNT)#define bfin_read_DMA1_2_X_COUNT()     bfin_read16(DMA1_2_X_COUNT)#define bfin_write_DMA1_2_X_COUNT(val) bfin_write16(DMA1_2_X_COUNT, val)#define pDMA1_2_Y_COUNT                ((uint16_t volatile *)DMA1_2_Y_COUNT)#define bfin_read_DMA1_2_Y_COUNT()     bfin_read16(DMA1_2_Y_COUNT)#define bfin_write_DMA1_2_Y_COUNT(val) bfin_write16(DMA1_2_Y_COUNT, val)#define pDMA1_2_X_MODIFY               ((uint16_t volatile *)DMA1_2_X_MODIFY)#define bfin_read_DMA1_2_X_MODIFY()    bfin_read16(DMA1_2_X_MODIFY)#define bfin_write_DMA1_2_X_MODIFY(val) bfin_write16(DMA1_2_X_MODIFY, val)#define pDMA1_2_Y_MODIFY               ((uint16_t volatile *)DMA1_2_Y_MODIFY)#define bfin_read_DMA1_2_Y_MODIFY()    bfin_read16(DMA1_2_Y_MODIFY)#define bfin_write_DMA1_2_Y_MODIFY(val) bfin_write16(DMA1_2_Y_MODIFY, val)#define pDMA1_2_CURR_DESC_PTR          ((void * volatile *)DMA1_2_CURR_DESC_PTR)#define bfin_read_DMA1_2_CURR_DESC_PTR() bfin_readPTR(DMA1_2_CURR_DESC_PTR)#define bfin_write_DMA1_2_CURR_DESC_PTR(val) bfin_writePTR(DMA1_2_CURR_DESC_PTR, val)#define pDMA1_2_CURR_ADDR              ((void * volatile *)DMA1_2_CURR_ADDR)
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