adsp-edn-dual-core-extended_def.h

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#define DMA2_2_IRQ_STATUS              0xFFC00CA8
#define DMA2_2_PERIPHERAL_MAP          0xFFC00CAC
#define DMA2_3_CONFIG                  0xFFC00CC8
#define DMA2_3_NEXT_DESC_PTR           0xFFC00CC0
#define DMA2_3_START_ADDR              0xFFC00CC4
#define DMA2_3_X_COUNT                 0xFFC00CD0
#define DMA2_3_Y_COUNT                 0xFFC00CD8
#define DMA2_3_X_MODIFY                0xFFC00CD4
#define DMA2_3_Y_MODIFY                0xFFC00CDC
#define DMA2_3_CURR_DESC_PTR           0xFFC00CE0
#define DMA2_3_CURR_ADDR               0xFFC00CE4
#define DMA2_3_CURR_X_COUNT            0xFFC00CF0
#define DMA2_3_CURR_Y_COUNT            0xFFC00CF8
#define DMA2_3_IRQ_STATUS              0xFFC00CE8
#define DMA2_3_PERIPHERAL_MAP          0xFFC00CEC
#define DMA2_4_CONFIG                  0xFFC00D08
#define DMA2_4_NEXT_DESC_PTR           0xFFC00D00
#define DMA2_4_START_ADDR              0xFFC00D04
#define DMA2_4_X_COUNT                 0xFFC00D10
#define DMA2_4_Y_COUNT                 0xFFC00D18
#define DMA2_4_X_MODIFY                0xFFC00D14
#define DMA2_4_Y_MODIFY                0xFFC00D1C
#define DMA2_4_CURR_DESC_PTR           0xFFC00D20
#define DMA2_4_CURR_ADDR               0xFFC00D24
#define DMA2_4_CURR_X_COUNT            0xFFC00D30
#define DMA2_4_CURR_Y_COUNT            0xFFC00D38
#define DMA2_4_IRQ_STATUS              0xFFC00D28
#define DMA2_4_PERIPHERAL_MAP          0xFFC00D2C
#define DMA2_5_CONFIG                  0xFFC00D48
#define DMA2_5_NEXT_DESC_PTR           0xFFC00D40
#define DMA2_5_START_ADDR              0xFFC00D44
#define DMA2_5_X_COUNT                 0xFFC00D50
#define DMA2_5_Y_COUNT                 0xFFC00D58
#define DMA2_5_X_MODIFY                0xFFC00D54
#define DMA2_5_Y_MODIFY                0xFFC00D5C
#define DMA2_5_CURR_DESC_PTR           0xFFC00D60
#define DMA2_5_CURR_ADDR               0xFFC00D64
#define DMA2_5_CURR_X_COUNT            0xFFC00D70
#define DMA2_5_CURR_Y_COUNT            0xFFC00D78
#define DMA2_5_IRQ_STATUS              0xFFC00D68
#define DMA2_5_PERIPHERAL_MAP          0xFFC00D6C
#define DMA2_6_CONFIG                  0xFFC00D88
#define DMA2_6_NEXT_DESC_PTR           0xFFC00D80
#define DMA2_6_START_ADDR              0xFFC00D84
#define DMA2_6_X_COUNT                 0xFFC00D90
#define DMA2_6_Y_COUNT                 0xFFC00D98
#define DMA2_6_X_MODIFY                0xFFC00D94
#define DMA2_6_Y_MODIFY                0xFFC00D9C
#define DMA2_6_CURR_DESC_PTR           0xFFC00DA0
#define DMA2_6_CURR_ADDR               0xFFC00DA4
#define DMA2_6_CURR_X_COUNT            0xFFC00DB0
#define DMA2_6_CURR_Y_COUNT            0xFFC00DB8
#define DMA2_6_IRQ_STATUS              0xFFC00DA8
#define DMA2_6_PERIPHERAL_MAP          0xFFC00DAC
#define DMA2_7_CONFIG                  0xFFC00DC8
#define DMA2_7_NEXT_DESC_PTR           0xFFC00DC0
#define DMA2_7_START_ADDR              0xFFC00DC4
#define DMA2_7_X_COUNT                 0xFFC00DD0
#define DMA2_7_Y_COUNT                 0xFFC00DD8
#define DMA2_7_X_MODIFY                0xFFC00DD4
#define DMA2_7_Y_MODIFY                0xFFC00DDC
#define DMA2_7_CURR_DESC_PTR           0xFFC00DE0
#define DMA2_7_CURR_ADDR               0xFFC00DE4
#define DMA2_7_CURR_X_COUNT            0xFFC00DF0
#define DMA2_7_CURR_Y_COUNT            0xFFC00DF8
#define DMA2_7_IRQ_STATUS              0xFFC00DE8
#define DMA2_7_PERIPHERAL_MAP          0xFFC00DEC
#define DMA2_8_CONFIG                  0xFFC00E08
#define DMA2_8_NEXT_DESC_PTR           0xFFC00E00
#define DMA2_8_START_ADDR              0xFFC00E04
#define DMA2_8_X_COUNT                 0xFFC00E10
#define DMA2_8_Y_COUNT                 0xFFC00E18
#define DMA2_8_X_MODIFY                0xFFC00E14
#define DMA2_8_Y_MODIFY                0xFFC00E1C
#define DMA2_8_CURR_DESC_PTR           0xFFC00E20
#define DMA2_8_CURR_ADDR               0xFFC00E24
#define DMA2_8_CURR_X_COUNT            0xFFC00E30
#define DMA2_8_CURR_Y_COUNT            0xFFC00E38
#define DMA2_8_IRQ_STATUS              0xFFC00E28
#define DMA2_8_PERIPHERAL_MAP          0xFFC00E2C
#define DMA2_9_CONFIG                  0xFFC00E48
#define DMA2_9_NEXT_DESC_PTR           0xFFC00E40
#define DMA2_9_START_ADDR              0xFFC00E44
#define DMA2_9_X_COUNT                 0xFFC00E50
#define DMA2_9_Y_COUNT                 0xFFC00E58
#define DMA2_9_X_MODIFY                0xFFC00E54
#define DMA2_9_Y_MODIFY                0xFFC00E5C
#define DMA2_9_CURR_DESC_PTR           0xFFC00E60
#define DMA2_9_CURR_ADDR               0xFFC00E64
#define DMA2_9_CURR_X_COUNT            0xFFC00E70
#define DMA2_9_CURR_Y_COUNT            0xFFC00E78
#define DMA2_9_IRQ_STATUS              0xFFC00E68
#define DMA2_9_PERIPHERAL_MAP          0xFFC00E6C
#define DMA2_10_CONFIG                 0xFFC00E88
#define DMA2_10_NEXT_DESC_PTR          0xFFC00E80
#define DMA2_10_START_ADDR             0xFFC00E84
#define DMA2_10_X_COUNT                0xFFC00E90
#define DMA2_10_Y_COUNT                0xFFC00E98
#define DMA2_10_X_MODIFY               0xFFC00E94
#define DMA2_10_Y_MODIFY               0xFFC00E9C
#define DMA2_10_CURR_DESC_PTR          0xFFC00EA0
#define DMA2_10_CURR_ADDR              0xFFC00EA4
#define DMA2_10_CURR_X_COUNT           0xFFC00EB0
#define DMA2_10_CURR_Y_COUNT           0xFFC00EB8
#define DMA2_10_IRQ_STATUS             0xFFC00EA8
#define DMA2_10_PERIPHERAL_MAP         0xFFC00EAC
#define DMA2_11_CONFIG                 0xFFC00EC8
#define DMA2_11_NEXT_DESC_PTR          0xFFC00EC0
#define DMA2_11_START_ADDR             0xFFC00EC4
#define DMA2_11_X_COUNT                0xFFC00ED0
#define DMA2_11_Y_COUNT                0xFFC00ED8
#define DMA2_11_X_MODIFY               0xFFC00ED4
#define DMA2_11_Y_MODIFY               0xFFC00EDC
#define DMA2_11_CURR_DESC_PTR          0xFFC00EE0
#define DMA2_11_CURR_ADDR              0xFFC00EE4
#define DMA2_11_CURR_X_COUNT           0xFFC00EF0
#define DMA2_11_CURR_Y_COUNT           0xFFC00EF8
#define DMA2_11_IRQ_STATUS             0xFFC00EE8
#define DMA2_11_PERIPHERAL_MAP         0xFFC00EEC
#define IMDMA_S0_CONFIG                0xFFC01848
#define IMDMA_S0_NEXT_DESC_PTR         0xFFC01840
#define IMDMA_S0_START_ADDR            0xFFC01844
#define IMDMA_S0_X_COUNT               0xFFC01850
#define IMDMA_S0_Y_COUNT               0xFFC01858
#define IMDMA_S0_X_MODIFY              0xFFC01854
#define IMDMA_S0_Y_MODIFY              0xFFC0185C
#define IMDMA_S0_CURR_DESC_PTR         0xFFC01860
#define IMDMA_S0_CURR_ADDR             0xFFC01864
#define IMDMA_S0_CURR_X_COUNT          0xFFC01870
#define IMDMA_S0_CURR_Y_COUNT          0xFFC01878
#define IMDMA_S0_IRQ_STATUS            0xFFC01868
#define IMDMA_D0_CONFIG                0xFFC01808
#define IMDMA_D0_NEXT_DESC_PTR         0xFFC01800
#define IMDMA_D0_START_ADDR            0xFFC01804
#define IMDMA_D0_X_COUNT               0xFFC01810
#define IMDMA_D0_Y_COUNT               0xFFC01818
#define IMDMA_D0_X_MODIFY              0xFFC01814
#define IMDMA_D0_Y_MODIFY              0xFFC0181C
#define IMDMA_D0_CURR_DESC_PTR         0xFFC01820
#define IMDMA_D0_CURR_ADDR             0xFFC01824
#define IMDMA_D0_CURR_X_COUNT          0xFFC01830
#define IMDMA_D0_CURR_Y_COUNT          0xFFC01838
#define IMDMA_D0_IRQ_STATUS            0xFFC01828
#define IMDMA_S1_CONFIG                0xFFC018C8
#define IMDMA_S1_NEXT_DESC_PTR         0xFFC018C0
#define IMDMA_S1_START_ADDR            0xFFC018C4
#define IMDMA_S1_X_COUNT               0xFFC018D0
#define IMDMA_S1_Y_COUNT               0xFFC018D8
#define IMDMA_S1_X_MODIFY              0xFFC018D4
#define IMDMA_S1_Y_MODIFY              0xFFC018DC
#define IMDMA_S1_CURR_DESC_PTR         0xFFC018E0
#define IMDMA_S1_CURR_ADDR             0xFFC018E4
#define IMDMA_S1_CURR_X_COUNT          0xFFC018F0
#define IMDMA_S1_CURR_Y_COUNT          0xFFC018F8
#define IMDMA_S1_IRQ_STATUS            0xFFC018E8
#define IMDMA_D1_CONFIG                0xFFC01888
#define IMDMA_D1_NEXT_DESC_PTR         0xFFC01880
#define IMDMA_D1_START_ADDR            0xFFC01884
#define IMDMA_D1_X_COUNT               0xFFC01890
#define IMDMA_D1_Y_COUNT               0xFFC01898
#define IMDMA_D1_X_MODIFY              0xFFC01894
#define IMDMA_D1_Y_MODIFY              0xFFC0189C
#define IMDMA_D1_CURR_DESC_PTR         0xFFC018A0
#define IMDMA_D1_CURR_ADDR             0xFFC018A4
#define IMDMA_D1_CURR_X_COUNT          0xFFC018B0
#define IMDMA_D1_CURR_Y_COUNT          0xFFC018B8
#define IMDMA_D1_IRQ_STATUS            0xFFC018A8
#define MDMA1_S0_CONFIG                0xFFC01F48
#define MDMA1_S0_NEXT_DESC_PTR         0xFFC01F40
#define MDMA1_S0_START_ADDR            0xFFC01F44
#define MDMA1_S0_X_COUNT               0xFFC01F50
#define MDMA1_S0_Y_COUNT               0xFFC01F58
#define MDMA1_S0_X_MODIFY              0xFFC01F54
#define MDMA1_S0_Y_MODIFY              0xFFC01F5C
#define MDMA1_S0_CURR_DESC_PTR         0xFFC01F60
#define MDMA1_S0_CURR_ADDR             0xFFC01F64
#define MDMA1_S0_CURR_X_COUNT          0xFFC01F70
#define MDMA1_S0_CURR_Y_COUNT          0xFFC01F78
#define MDMA1_S0_IRQ_STATUS            0xFFC01F68
#define MDMA1_S0_PERIPHERAL_MAP        0xFFC01F6C
#define MDMA1_D0_CONFIG                0xFFC01F08
#define MDMA1_D0_NEXT_DESC_PTR         0xFFC01F00
#define MDMA1_D0_START_ADDR            0xFFC01F04
#define MDMA1_D0_X_COUNT               0xFFC01F10
#define MDMA1_D0_Y_COUNT               0xFFC01F18
#define MDMA1_D0_X_MODIFY              0xFFC01F14
#define MDMA1_D0_Y_MODIFY              0xFFC01F1C
#define MDMA1_D0_CURR_DESC_PTR         0xFFC01F20
#define MDMA1_D0_CURR_ADDR             0xFFC01F24
#define MDMA1_D0_CURR_X_COUNT          0xFFC01F30
#define MDMA1_D0_CURR_Y_COUNT          0xFFC01F38
#define MDMA1_D0_IRQ_STATUS            0xFFC01F28
#define MDMA1_D0_PERIPHERAL_MAP        0xFFC01F2C
#define MDMA1_S1_CONFIG                0xFFC01FC8
#define MDMA1_S1_NEXT_DESC_PTR         0xFFC01FC0
#define MDMA1_S1_START_ADDR            0xFFC01FC4
#define MDMA1_S1_X_COUNT               0xFFC01FD0
#define MDMA1_S1_Y_COUNT               0xFFC01FD8
#define MDMA1_S1_X_MODIFY              0xFFC01FD4
#define MDMA1_S1_Y_MODIFY              0xFFC01FDC
#define MDMA1_S1_CURR_DESC_PTR         0xFFC01FE0
#define MDMA1_S1_CURR_ADDR             0xFFC01FE4
#define MDMA1_S1_CURR_X_COUNT          0xFFC01FF0
#define MDMA1_S1_CURR_Y_COUNT          0xFFC01FF8
#define MDMA1_S1_IRQ_STATUS            0xFFC01FE8
#define MDMA1_S1_PERIPHERAL_MAP        0xFFC01FEC
#define MDMA1_D1_CONFIG                0xFFC01F88
#define MDMA1_D1_NEXT_DESC_PTR         0xFFC01F80
#define MDMA1_D1_START_ADDR            0xFFC01F84
#define MDMA1_D1_X_COUNT               0xFFC01F90
#define MDMA1_D1_Y_COUNT               0xFFC01F98
#define MDMA1_D1_X_MODIFY              0xFFC01F94
#define MDMA1_D1_Y_MODIFY              0xFFC01F9C
#define MDMA1_D1_CURR_DESC_PTR         0xFFC01FA0
#define MDMA1_D1_CURR_ADDR             0xFFC01FA4
#define MDMA1_D1_CURR_X_COUNT          0xFFC01FB0
#define MDMA1_D1_CURR_Y_COUNT          0xFFC01FB8
#define MDMA1_D1_IRQ_STATUS            0xFFC01FA8
#define MDMA1_D1_PERIPHERAL_MAP        0xFFC01FAC
#define MDMA2_S0_CONFIG                0xFFC00F48
#define MDMA2_S0_NEXT_DESC_PTR         0xFFC00F40
#define MDMA2_S0_START_ADDR            0xFFC00F44
#define MDMA2_S0_X_COUNT               0xFFC00F50
#define MDMA2_S0_Y_COUNT               0xFFC00F58