adsp-edn-bf52x-extended_def.h

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#define MDMA_S1_X_MODIFY               0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */
#define MDMA_S1_Y_COUNT                0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */
#define MDMA_S1_Y_MODIFY               0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */
#define MDMA_S1_CURR_DESC_PTR          0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
#define MDMA_S1_CURR_ADDR              0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */
#define MDMA_S1_IRQ_STATUS             0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */
#define MDMA_S1_PERIPHERAL_MAP         0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */
#define MDMA_S1_CURR_X_COUNT           0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */
#define MDMA_S1_CURR_Y_COUNT           0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */
#define MDMA_D1_NEXT_DESC_PTR          0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
#define MDMA_D1_START_ADDR             0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */
#define MDMA_D1_CONFIG                 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */
#define MDMA_D1_X_COUNT                0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */
#define MDMA_D1_X_MODIFY               0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */
#define MDMA_D1_Y_COUNT                0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */
#define MDMA_D1_Y_MODIFY               0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */
#define MDMA_D1_CURR_DESC_PTR          0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
#define MDMA_D1_CURR_ADDR              0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */
#define MDMA_D1_IRQ_STATUS             0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */
#define MDMA_D1_PERIPHERAL_MAP         0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */
#define MDMA_D1_CURR_X_COUNT           0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */
#define MDMA_D1_CURR_Y_COUNT           0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */
#define PPI_CONTROL                    0xFFC01000 /* PPI Control Register */
#define PPI_STATUS                     0xFFC01004 /* PPI Status Register */
#define PPI_COUNT                      0xFFC01008 /* PPI Transfer Count Register */
#define PPI_DELAY                      0xFFC0100C /* PPI Delay Count Register */
#define PPI_FRAME                      0xFFC01010 /* PPI Frame Length Register */
#define TWI_CLKDIV                     0xFFC01400 /* Serial Clock Divider Register */
#define TWI_CONTROL                    0xFFC01404 /* TWI Control Register */
#define TWI_SLAVE_CTL                  0xFFC01408 /* Slave Mode Control Register */
#define TWI_SLAVE_STAT                 0xFFC0140C /* Slave Mode Status Register */
#define TWI_SLAVE_ADDR                 0xFFC01410 /* Slave Mode Address Register */
#define TWI_MASTER_CTL                 0xFFC01414 /* Master Mode Control Register */
#define TWI_MASTER_STAT                0xFFC01418 /* Master Mode Status Register */
#define TWI_MASTER_ADDR                0xFFC0141C /* Master Mode Address Register */
#define TWI_INT_STAT                   0xFFC01420 /* TWI Interrupt Status Register */
#define TWI_INT_MASK                   0xFFC01424 /* TWI Master Interrupt Mask Register */
#define TWI_FIFO_CTL                   0xFFC01428 /* FIFO Control Register */
#define TWI_FIFO_STAT                  0xFFC0142C /* FIFO Status Register */
#define TWI_XMT_DATA8                  0xFFC01480 /* FIFO Transmit Data Single Byte Register */
#define TWI_XMT_DATA16                 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
#define TWI_RCV_DATA8                  0xFFC01488 /* FIFO Receive Data Single Byte Register */
#define TWI_RCV_DATA16                 0xFFC0148C /* FIFO Receive Data Double Byte Register */
#define PORTGIO                        0xFFC01500 /* Port G I/O Pin State Specify Register */
#define PORTGIO_CLEAR                  0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */
#define PORTGIO_SET                    0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */
#define PORTGIO_TOGGLE                 0xFFC0150C /* Port G I/O Pin State Toggle Register */
#define PORTGIO_MASKA                  0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */
#define PORTGIO_MASKA_CLEAR            0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */
#define PORTGIO_MASKA_SET              0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */
#define PORTGIO_MASKA_TOGGLE           0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */
#define PORTGIO_MASKB                  0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */
#define PORTGIO_MASKB_CLEAR            0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */
#define PORTGIO_MASKB_SET              0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */
#define PORTGIO_MASKB_TOGGLE           0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */
#define PORTGIO_DIR                    0xFFC01530 /* Port G I/O Direction Register */
#define PORTGIO_POLAR                  0xFFC01534 /* Port G I/O Source Polarity Register */
#define PORTGIO_EDGE                   0xFFC01538 /* Port G I/O Source Sensitivity Register */
#define PORTGIO_BOTH                   0xFFC0153C /* Port G I/O Set on BOTH Edges Register */
#define PORTGIO_INEN                   0xFFC01540 /* Port G I/O Input Enable Register */
#define PORTHIO                        0xFFC01700 /* Port H I/O Pin State Specify Register */
#define PORTHIO_CLEAR                  0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */
#define PORTHIO_SET                    0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */
#define PORTHIO_TOGGLE                 0xFFC0170C /* Port H I/O Pin State Toggle Register */
#define PORTHIO_MASKA                  0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */
#define PORTHIO_MASKA_CLEAR            0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */
#define PORTHIO_MASKA_SET              0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */
#define PORTHIO_MASKA_TOGGLE           0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */
#define PORTHIO_MASKB                  0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */
#define PORTHIO_MASKB_CLEAR            0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */
#define PORTHIO_MASKB_SET              0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */
#define PORTHIO_MASKB_TOGGLE           0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */
#define PORTHIO_DIR                    0xFFC01730 /* Port H I/O Direction Register */
#define PORTHIO_POLAR                  0xFFC01734 /* Port H I/O Source Polarity Register */
#define PORTHIO_EDGE                   0xFFC01738 /* Port H I/O Source Sensitivity Register */
#define PORTHIO_BOTH                   0xFFC0173C /* Port H I/O Set on BOTH Edges Register */
#define PORTHIO_INEN                   0xFFC01740 /* Port H I/O Input Enable Register */
#define UART1_THR                      0xFFC02000 /* Transmit Holding register */
#define UART1_RBR                      0xFFC02000 /* Receive Buffer register */
#define UART1_DLL                      0xFFC02000 /* Divisor Latch (Low-Byte) */
#define UART1_IER                      0xFFC02004 /* Interrupt Enable Register */
#define UART1_DLH                      0xFFC02004 /* Divisor Latch (High-Byte) */
#define UART1_IIR                      0xFFC02008 /* Interrupt Identification Register */
#define UART1_LCR                      0xFFC0200C /* Line Control Register */
#define UART1_MCR                      0xFFC02010 /* Modem Control Register */
#define UART1_LSR                      0xFFC02014 /* Line Status Register */
#define UART1_MSR                      0xFFC02018 /* Modem Status Register */
#define UART1_SCR                      0xFFC0201C /* SCR Scratch Register */
#define UART1_GCTL                     0xFFC02024 /* Global Control Register */
#define PORTF_FER                      0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */
#define PORTG_FER                      0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */
#define PORTH_FER                      0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */
#define HMDMA0_CONTROL                 0xFFC03300 /* Handshake MDMA0 Control Register */
#define HMDMA0_ECINIT                  0xFFC03304 /* HMDMA0 Initial Edge Count Register */
#define HMDMA0_BCINIT                  0xFFC03308 /* HMDMA0 Initial Block Count Register */
#define HMDMA0_ECURGENT                0xFFC0330C /* HMDMA0 Urgent Edge Count Threshhold Register */
#define HMDMA0_ECOVERFLOW              0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */
#define HMDMA0_ECOUNT                  0xFFC03314 /* HMDMA0 Current Edge Count Register */
#define HMDMA0_BCOUNT                  0xFFC03318 /* HMDMA0 Current Block Count Register */
#define HMDMA1_CONTROL                 0xFFC03340 /* Handshake MDMA1 Control Register */
#define HMDMA1_ECINIT                  0xFFC03344 /* HMDMA1 Initial Edge Count Register */
#define HMDMA1_BCINIT                  0xFFC03348 /* HMDMA1 Initial Block Count Register */
#define HMDMA1_ECURGENT                0xFFC0334C /* HMDMA1 Urgent Edge Count Threshhold Register */
#define HMDMA1_ECOVERFLOW              0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */
#define HMDMA1_ECOUNT                  0xFFC03354 /* HMDMA1 Current Edge Count Register */
#define HMDMA1_BCOUNT                  0xFFC03358 /* HMDMA1 Current Block Count Register */
#define PORTF_MUX                      0xFFC03210 /* Port F mux control */
#define PORTG_MUX                      0xFFC03214 /* Port G mux control */
#define PORTH_MUX                      0xFFC03218 /* Port H mux control */
#define PORTF_DRIVE                    0xFFC03220 /* Port F drive strength control */
#define PORTG_DRIVE                    0xFFC03224 /* Port G drive strength control */
#define PORTH_DRIVE                    0xFFC03228 /* Port H drive strength control */
#define PORTF_SLEW                     0xFFC03230 /* Port F slew control */
#define PORTG_SLEW                     0xFFC03234 /* Port G slew control */
#define PORTH_SLEW                     0xFFC03238 /* Port H slew control */
#define PORTF_HYSTERESIS               0xFFC03240 /* Port F Schmitt trigger control */
#define PORTG_HYSTERESIS               0xFFC03244 /* Port G Schmitt trigger control */
#define PORTH_HYSTERESIS               0xFFC03248 /* Port H Schmitt trigger control */
#define NONGPIO_DRIVE                  0xFFC03280 /* Non-GPIO Port drive strength control */
#define NONGPIO_SLEW                   0xFFC03284 /* Non-GPIO Port slew control */
#define NONGPIO_HYSTERESIS             0xFFC03288 /* Non-GPIO Port Schmitt trigger control */
#define HOST_CONTROL                   0xFFC03400 /* HOST Control Register */
#define HOST_STATUS                    0xFFC03404 /* HOST Status Register */
#define HOST_TIMEOUT                   0xFFC03408 /* HOST Acknowledge Mode Timeout Register */
#define CNT_CONFIG                     0xFFC03500 /* Configuration/Control Register */
#define CNT_IMASK                      0xFFC03504 /* Interrupt Mask Register */
#define CNT_STATUS                     0xFFC03508 /* Status Register */
#define CNT_COMMAND                    0xFFC0350C /* Command Register */
#define CNT_DEBOUNCE                   0xFFC03510 /* Debounce Prescaler Register */
#define CNT_COUNTER                    0xFFC03514 /* Counter Register */
#define CNT_MAX                        0xFFC03518 /* Maximal Count Boundary Value Register */
#define CNT_MIN                        0xFFC0351C /* Minimal Count Boundary Value Register */
#define OTP_CONTROL                    0xFFC03600 /* OTP/Fuse Control Register */
#define OTP_BEN                        0xFFC03604 /* OTP/Fuse Byte Enable */
#define OTP_STATUS                     0xFFC03608 /* OTP/Fuse Status */
#define OTP_TIMING                     0xFFC0360C /* OTP/Fuse Access Timing */
#define SECURE_SYSSWT                  0xFFC03620 /* Secure System Switches */
#define SECURE_CONTROL                 0xFFC03624 /* Secure Control */
#define SECURE_STATUS                  0xFFC03628 /* Secure Status */
#define OTP_DATA0                      0xFFC03680 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
#define OTP_DATA1                      0xFFC03684 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
#define OTP_DATA2                      0xFFC03688 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
#define OTP_DATA3                      0xFFC0368C /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
#define NFC_CTL                        0xFFC03700 /* NAND Control Register */
#define NFC_STAT                       0xFFC03704 /* NAND Status Register */
#define NFC_IRQSTAT                    0xFFC03708 /* NAND Interrupt Status Register */
#define NFC_IRQMASK                    0xFFC0370C /* NAND Interrupt Mask Register */
#define NFC_ECC0                       0xFFC03710 /* NAND ECC Register 0 */
#define NFC_ECC1                       0xFFC03714 /* NAND ECC Register 1 */
#define NFC_ECC2                       0xFFC03718 /* NAND ECC Register 2 */
#define NFC_ECC3                       0xFFC0371C /* NAND ECC Register 3 */
#define NFC_COUNT                      0xFFC03720 /* NAND ECC Count Register */
#define NFC_RST                        0xFFC03724 /* NAND ECC Reset Register */
#define NFC_PGCTL                      0xFFC03728 /* NAND Page Control Register */
#define NFC_READ                       0xFFC0372C /* NAND Read Data Register */
#define NFC_ADDR                       0xFFC03740 /* NAND Address Register */
#define NFC_CMD                        0xFFC03744 /* NAND Command Register */
#define NFC_DATA_WR                    0xFFC03748 /* NAND Data Write Register */
#define NFC_DATA_RD                    0xFFC0374C /* NAND Data Read Register */
#define TBUFCTL                        0xFFE06000 /* Trace Buffer Control Register */
#define TBUFSTAT                       0xFFE06004 /* Trace Buffer Status Register */
#define TBUF                           0xFFE06100 /* Trace Buffer */
#define PFCTL                          0xFFE08000
#define PFCNTR0                        0xFFE08100
#define PFCNTR1                        0xFFE08104
#define DMA_TC_CNT                     0xFFC00B0C
#define DMA_TC_PER                     0xFFC00B10

#endif /* __BFIN_DEF_ADSP_EDN_BF52x_extended__ */