bf524_def.h

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#define USB_EP7_FIFO                   0xFFC038B8 /* Endpoint 7 FIFO */
#define USB_OTG_DEV_CTL                0xFFC03900 /* OTG Device Control Register */
#define USB_OTG_VBUS_IRQ               0xFFC03904 /* OTG VBUS Control Interrupts */
#define USB_OTG_VBUS_MASK              0xFFC03908 /* VBUS Control Interrupt Enable */
#define USB_LINKINFO                   0xFFC03948 /* Enables programming of some PHY-side delays */
#define USB_VPLEN                      0xFFC0394C /* Determines duration of VBUS pulse for VBUS charging */
#define USB_HS_EOF1                    0xFFC03950 /* Time buffer for High-Speed transactions */
#define USB_FS_EOF1                    0xFFC03954 /* Time buffer for Full-Speed transactions */
#define USB_LS_EOF1                    0xFFC03958 /* Time buffer for Low-Speed transactions */
#define USB_APHY_CNTRL                 0xFFC039E0 /* Register that increases visibility of Analog PHY */
#define USB_APHY_CALIB                 0xFFC039E4 /* Register used to set some calibration values */
#define USB_APHY_CNTRL2                0xFFC039E8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
#define USB_PHY_TEST                   0xFFC039EC /* Used for reducing simulation time and simplifies FIFO testability */
#define USB_PLLOSC_CTRL                0xFFC039F0 /* Used to program different parameters for USB PLL and Oscillator */
#define USB_SRP_CLKDIV                 0xFFC039F4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
#define USB_EP_NI0_TXMAXP              0xFFC03A00 /* Maximum packet size for Host Tx endpoint0 */
#define USB_EP_NI0_TXCSR               0xFFC03A04 /* Control Status register for endpoint 0 */
#define USB_EP_NI0_RXMAXP              0xFFC03A08 /* Maximum packet size for Host Rx endpoint0 */
#define USB_EP_NI0_RXCSR               0xFFC03A0C /* Control Status register for Host Rx endpoint0 */
#define USB_EP_NI0_RXCOUNT             0xFFC03A10 /* Number of bytes received in endpoint 0 FIFO */
#define USB_EP_NI0_TXTYPE              0xFFC03A14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
#define USB_EP_NI0_TXINTERVAL          0xFFC03A18 /* Sets the NAK response timeout on Endpoint 0 */
#define USB_EP_NI0_RXTYPE              0xFFC03A1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
#define USB_EP_NI0_RXINTERVAL          0xFFC03A20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
#define USB_EP_NI0_TXCOUNT             0xFFC03A28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
#define USB_EP_NI1_TXMAXP              0xFFC03A40 /* Maximum packet size for Host Tx endpoint1 */
#define USB_EP_NI1_TXCSR               0xFFC03A44 /* Control Status register for endpoint1 */
#define USB_EP_NI1_RXMAXP              0xFFC03A48 /* Maximum packet size for Host Rx endpoint1 */
#define USB_EP_NI1_RXCSR               0xFFC03A4C /* Control Status register for Host Rx endpoint1 */
#define USB_EP_NI1_RXCOUNT             0xFFC03A50 /* Number of bytes received in endpoint1 FIFO */
#define USB_EP_NI1_TXTYPE              0xFFC03A54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
#define USB_EP_NI1_TXINTERVAL          0xFFC03A58 /* Sets the NAK response timeout on Endpoint1 */
#define USB_EP_NI1_RXTYPE              0xFFC03A5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
#define USB_EP_NI1_RXINTERVAL          0xFFC03A60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
#define USB_EP_NI1_TXCOUNT             0xFFC03A68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
#define USB_EP_NI2_TXMAXP              0xFFC03A80 /* Maximum packet size for Host Tx endpoint2 */
#define USB_EP_NI2_TXCSR               0xFFC03A84 /* Control Status register for endpoint2 */
#define USB_EP_NI2_RXMAXP              0xFFC03A88 /* Maximum packet size for Host Rx endpoint2 */
#define USB_EP_NI2_RXCSR               0xFFC03A8C /* Control Status register for Host Rx endpoint2 */
#define USB_EP_NI2_RXCOUNT             0xFFC03A90 /* Number of bytes received in endpoint2 FIFO */
#define USB_EP_NI2_TXTYPE              0xFFC03A94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
#define USB_EP_NI2_TXINTERVAL          0xFFC03A98 /* Sets the NAK response timeout on Endpoint2 */
#define USB_EP_NI2_RXTYPE              0xFFC03A9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
#define USB_EP_NI2_RXINTERVAL          0xFFC03AA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
#define USB_EP_NI2_TXCOUNT             0xFFC03AA8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
#define USB_EP_NI3_TXMAXP              0xFFC03AC0 /* Maximum packet size for Host Tx endpoint3 */
#define USB_EP_NI3_TXCSR               0xFFC03AC4 /* Control Status register for endpoint3 */
#define USB_EP_NI3_RXMAXP              0xFFC03AC8 /* Maximum packet size for Host Rx endpoint3 */
#define USB_EP_NI3_RXCSR               0xFFC03ACC /* Control Status register for Host Rx endpoint3 */
#define USB_EP_NI3_RXCOUNT             0xFFC03AD0 /* Number of bytes received in endpoint3 FIFO */
#define USB_EP_NI3_TXTYPE              0xFFC03AD4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
#define USB_EP_NI3_TXINTERVAL          0xFFC03AD8 /* Sets the NAK response timeout on Endpoint3 */
#define USB_EP_NI3_RXTYPE              0xFFC03ADC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
#define USB_EP_NI3_RXINTERVAL          0xFFC03AE0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
#define USB_EP_NI3_TXCOUNT             0xFFC03AE8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
#define USB_EP_NI4_TXMAXP              0xFFC03B00 /* Maximum packet size for Host Tx endpoint4 */
#define USB_EP_NI4_TXCSR               0xFFC03B04 /* Control Status register for endpoint4 */
#define USB_EP_NI4_RXMAXP              0xFFC03B08 /* Maximum packet size for Host Rx endpoint4 */
#define USB_EP_NI4_RXCSR               0xFFC03B0C /* Control Status register for Host Rx endpoint4 */
#define USB_EP_NI4_RXCOUNT             0xFFC03B10 /* Number of bytes received in endpoint4 FIFO */
#define USB_EP_NI4_TXTYPE              0xFFC03B14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
#define USB_EP_NI4_TXINTERVAL          0xFFC03B18 /* Sets the NAK response timeout on Endpoint4 */
#define USB_EP_NI4_RXTYPE              0xFFC03B1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
#define USB_EP_NI4_RXINTERVAL          0xFFC03B20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
#define USB_EP_NI4_TXCOUNT             0xFFC03B28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
#define USB_EP_NI5_TXMAXP              0xFFC03B40 /* Maximum packet size for Host Tx endpoint5 */
#define USB_EP_NI5_TXCSR               0xFFC03B44 /* Control Status register for endpoint5 */
#define USB_EP_NI5_RXMAXP              0xFFC03B48 /* Maximum packet size for Host Rx endpoint5 */
#define USB_EP_NI5_RXCSR               0xFFC03B4C /* Control Status register for Host Rx endpoint5 */
#define USB_EP_NI5_RXCOUNT             0xFFC03B50 /* Number of bytes received in endpoint5 FIFO */
#define USB_EP_NI5_TXTYPE              0xFFC03B54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
#define USB_EP_NI5_TXINTERVAL          0xFFC03B58 /* Sets the NAK response timeout on Endpoint5 */
#define USB_EP_NI5_RXTYPE              0xFFC03B5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
#define USB_EP_NI5_RXINTERVAL          0xFFC03B60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
#define USB_EP_NI5_TXCOUNT             0xFFC03B68 /* Number of bytes to be written to the endpoint5 Tx FIFO */
#define USB_EP_NI6_TXMAXP              0xFFC03B80 /* Maximum packet size for Host Tx endpoint6 */
#define USB_EP_NI6_TXCSR               0xFFC03B84 /* Control Status register for endpoint6 */
#define USB_EP_NI6_RXMAXP              0xFFC03B88 /* Maximum packet size for Host Rx endpoint6 */
#define USB_EP_NI6_RXCSR               0xFFC03B8C /* Control Status register for Host Rx endpoint6 */
#define USB_EP_NI6_RXCOUNT             0xFFC03B90 /* Number of bytes received in endpoint6 FIFO */
#define USB_EP_NI6_TXTYPE              0xFFC03B94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
#define USB_EP_NI6_TXINTERVAL          0xFFC03B98 /* Sets the NAK response timeout on Endpoint6 */
#define USB_EP_NI6_RXTYPE              0xFFC03B9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
#define USB_EP_NI6_RXINTERVAL          0xFFC03BA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
#define USB_EP_NI6_TXCOUNT             0xFFC03BA8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
#define USB_EP_NI7_TXMAXP              0xFFC03BC0 /* Maximum packet size for Host Tx endpoint7 */
#define USB_EP_NI7_TXCSR               0xFFC03BC4 /* Control Status register for endpoint7 */
#define USB_EP_NI7_RXMAXP              0xFFC03BC8 /* Maximum packet size for Host Rx endpoint7 */
#define USB_EP_NI7_RXCSR               0xFFC03BCC /* Control Status register for Host Rx endpoint7 */
#define USB_EP_NI7_RXCOUNT             0xFFC03BD0 /* Number of bytes received in endpoint7 FIFO */
#define USB_EP_NI7_TXTYPE              0xFFC03BD4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
#define USB_EP_NI7_TXINTERVAL          0xFFC03BD8 /* Sets the NAK response timeout on Endpoint7 */
#define USB_EP_NI7_RXTYPE              0xFFC03BDC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
#define USB_EP_NI7_RXINTERVAL          0xFFC03BF0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
#define USB_EP_NI7_TXCOUNT             0xFFC03BF8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
#define USB_DMA_INTERRUPT              0xFFC03C00 /* Indicates pending interrupts for the DMA channels */
#define USB_DMA0_CONTROL               0xFFC03C04 /* DMA master channel 0 configuration */
#define USB_DMA0_ADDRLOW               0xFFC03C08 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
#define USB_DMA0_ADDRHIGH              0xFFC03C0C /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
#define USB_DMA0_COUNTLOW              0xFFC03C10 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
#define USB_DMA0_COUNTHIGH             0xFFC03C14 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
#define USB_DMA1_CONTROL               0xFFC03C24 /* DMA master channel 1 configuration */
#define USB_DMA1_ADDRLOW               0xFFC03C28 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
#define USB_DMA1_ADDRHIGH              0xFFC03C2C /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
#define USB_DMA1_COUNTLOW              0xFFC03C30 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
#define USB_DMA1_COUNTHIGH             0xFFC03C34 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
#define USB_DMA2_CONTROL               0xFFC03C44 /* DMA master channel 2 configuration */
#define USB_DMA2_ADDRLOW               0xFFC03C48 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
#define USB_DMA2_ADDRHIGH              0xFFC03C4C /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
#define USB_DMA2_COUNTLOW              0xFFC03C50 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
#define USB_DMA2_COUNTHIGH             0xFFC03C54 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
#define USB_DMA3_CONTROL               0xFFC03C64 /* DMA master channel 3 configuration */
#define USB_DMA3_ADDRLOW               0xFFC03C68 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
#define USB_DMA3_ADDRHIGH              0xFFC03C6C /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
#define USB_DMA3_COUNTLOW              0xFFC03C70 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
#define USB_DMA3_COUNTHIGH             0xFFC03C74 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
#define USB_DMA4_CONTROL               0xFFC03C84 /* DMA master channel 4 configuration */
#define USB_DMA4_ADDRLOW               0xFFC03C88 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
#define USB_DMA4_ADDRHIGH              0xFFC03C8C /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
#define USB_DMA4_COUNTLOW              0xFFC03C90 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
#define USB_DMA4_COUNTHIGH             0xFFC03C94 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
#define USB_DMA5_CONTROL               0xFFC03CA4 /* DMA master channel 5 configuration */
#define USB_DMA5_ADDRLOW               0xFFC03CA8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
#define USB_DMA5_ADDRHIGH              0xFFC03CAC /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
#define USB_DMA5_COUNTLOW              0xFFC03CB0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
#define USB_DMA5_COUNTHIGH             0xFFC03CB4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
#define USB_DMA6_CONTROL               0xFFC03CC4 /* DMA master channel 6 configuration */
#define USB_DMA6_ADDRLOW               0xFFC03CC8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
#define USB_DMA6_ADDRHIGH              0xFFC03CCC /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
#define USB_DMA6_COUNTLOW              0xFFC03CD0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
#define USB_DMA6_COUNTHIGH             0xFFC03CD4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
#define USB_DMA7_CONTROL               0xFFC03CE4 /* DMA master channel 7 configuration */
#define USB_DMA7_ADDRLOW               0xFFC03CE8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
#define USB_DMA7_ADDRHIGH              0xFFC03CEC /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
#define USB_DMA7_COUNTLOW              0xFFC03CF0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
#define USB_DMA7_COUNTHIGH             0xFFC03CF4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */
#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1)
#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE)
#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */
#define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1)
#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE)
#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */
#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1)
#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE)
#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */
#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1)
#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE)
#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */
#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1)
#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE)

#endif /* __BFIN_DEF_ADSP_BF524_proc__ */