pong_top.sch

important paper cutting code

VERSION 6
BEGIN SCHEMATIC
    BEGIN ATTR DeviceFamilyName "spartan3"
        DELETE all:0
        EDITNAME all:0
        EDITTRAIT all:0
    END ATTR
    BEGIN NETLIST
        BEGIN SIGNAL seg_a
            BEGIN ATTR LOC "e14"
                VERILOG all:0 wsynth:1
                VHDL all:0 wa:1 wd:1
            END ATTR
        END SIGNAL
        BEGIN SIGNAL seg_b
            BEGIN ATTR LOC "g13"
                VERILOG all:0 wsynth:1
                VHDL all:0 wa:1 wd:1
            END ATTR
        END SIGNAL
        BEGIN SIGNAL seg_c
            BEGIN ATTR LOC "n15"
                VERILOG all:0 wsynth:1
                VHDL all:0 wa:1 wd:1
            END ATTR
        END SIGNAL
        BEGIN SIGNAL seg_d
            BEGIN ATTR LOC "p15"
                VERILOG all:0 wsynth:1
                VHDL all:0 wa:1 wd:1
            END ATTR
        END SIGNAL
        BEGIN SIGNAL seg_e
            BEGIN ATTR LOC "r16"
                VERILOG all:0 wsynth:1
                VHDL all:0 wa:1 wd:1
            END ATTR
        END SIGNAL
        BEGIN SIGNAL seg_f
            BEGIN ATTR LOC "f13"
                VERILOG all:0 wsynth:1
                VHDL all:0 wa:1 wd:1
            END ATTR
        END SIGNAL
        BEGIN SIGNAL seg_g
            BEGIN ATTR LOC "n16"
                VERILOG all:0 wsynth:1
                VHDL all:0 wa:1 wd:1
            END ATTR
        END SIGNAL
        BEGIN SIGNAL seg_dp
            BEGIN ATTR LOC "p16"
                VERILOG all:0 wsynth:1
                VHDL all:0 wa:1 wd:1
            END ATTR
        END SIGNAL
        BEGIN SIGNAL an(0)
            BEGIN ATTR LOC "d14"
                VERILOG all:0 wsynth:1
                VHDL all:0 wa:1 wd:1
            END ATTR
        END SIGNAL
        BEGIN SIGNAL an(1)
            BEGIN ATTR LOC "g14"
                VERILOG all:0 wsynth:1
                VHDL all:0 wa:1 wd:1
            END ATTR
        END SIGNAL
        BEGIN SIGNAL an(2)
            BEGIN ATTR LOC "f14"
                VERILOG all:0 wsynth:1
                VHDL all:0 wa:1 wd:1
            END ATTR
        END SIGNAL
        BEGIN SIGNAL an(3)
            BEGIN ATTR LOC "e13"
                VERILOG all:0 wsynth:1
                VHDL all:0 wa:1 wd:1
            END ATTR
        END SIGNAL
        BEGIN SIGNAL vga_red
            BEGIN ATTR LOC "r12"
                VERILOG all:0 wsynth:1
                VHDL all:0 wa:1 wd:1
            END ATTR
        END SIGNAL
        BEGIN SIGNAL vga_green
            BEGIN ATTR LOC "t12"
                VERILOG all:0 wsynth:1
                VHDL all:0 wa:1 wd:1
            END ATTR
        END SIGNAL
        BEGIN SIGNAL vga_blue
            BEGIN ATTR LOC "r11"
                VERILOG all:0 wsynth:1
                VHDL all:0 wa:1 wd:1
            END ATTR
        END SIGNAL
        BEGIN SIGNAL vga_hs
            BEGIN ATTR LOC "r9"
                VERILOG all:0 wsynth:1
                VHDL all:0 wa:1 wd:1
            END ATTR
        END SIGNAL
        BEGIN SIGNAL vga_vs
            BEGIN ATTR LOC "t10"
                VERILOG all:0 wsynth:1
                VHDL all:0 wa:1 wd:1
            END ATTR
        END SIGNAL
        BEGIN SIGNAL ps2c
            BEGIN ATTR LOC "m16"
                VERILOG all:0 wsynth:1
                VHDL all:0 wa:1 wd:1
            END ATTR
        END SIGNAL
        BEGIN SIGNAL clk_ic4
            BEGIN ATTR LOC "t9"
                VERILOG all:0 wsynth:1
                VHDL all:0 wa:1 wd:1
            END ATTR
        END SIGNAL
        BEGIN SIGNAL ps2d
            BEGIN ATTR LOC "m15"
                VERILOG all:0 wsynth:1
                VHDL all:0 wa:1 wd:1
            END ATTR
        END SIGNAL
        SIGNAL an(3:0)
        SIGNAL ld(7:0)
        BEGIN SIGNAL btn3
            BEGIN ATTR LOC "l14"
                VERILOG all:0 wsynth:1
                VHDL all:0 wa:1 wd:1
            END ATTR
        END SIGNAL
        BEGIN SIGNAL ld(0)
            BEGIN ATTR LOC "k12"
                VERILOG all:0 wsynth:1
                VHDL all:0 wa:1 wd:1
            END ATTR
        END SIGNAL
        BEGIN SIGNAL ld(1)
            BEGIN ATTR LOC "p14"
                VERILOG all:0 wsynth:1
                VHDL all:0 wa:1 wd:1
            END ATTR
        END SIGNAL
        BEGIN SIGNAL ld(2)
            BEGIN ATTR LOC "l12"
                VERILOG all:0 wsynth:1
                VHDL all:0 wa:1 wd:1
            END ATTR
        END SIGNAL
        BEGIN SIGNAL ld(4)
            BEGIN ATTR LOC "p13"
                VERILOG all:0 wsynth:1
                VHDL all:0 wa:1 wd:1
            END ATTR
        END SIGNAL
        BEGIN SIGNAL ld(5)
            BEGIN ATTR LOC "n12"
                VERILOG all:0 wsynth:1
                VHDL all:0 wa:1 wd:1
            END ATTR
        END SIGNAL
        BEGIN SIGNAL ld(6)
            BEGIN ATTR LOC "p12"
                VERILOG all:0 wsynth:1
                VHDL all:0 wa:1 wd:1
            END ATTR
        END SIGNAL
        BEGIN SIGNAL ld(7)
            BEGIN ATTR LOC "p11"
                VERILOG all:0 wsynth:1
                VHDL all:0 wa:1 wd:1
            END ATTR
        END SIGNAL
        BEGIN SIGNAL ld(3)
            BEGIN ATTR LOC "n14"
                VERILOG all:0 wsynth:1
                VHDL all:0 wa:1 wd:1
            END ATTR
        END SIGNAL
        SIGNAL XLXN_31(1:0)
        SIGNAL hsync
        SIGNAL vsync
        SIGNAL lf_dir(1:0)
        SIGNAL rt_dir(1:0)
        SIGNAL serve
        SIGNAL seg_a,seg_b,seg_c,seg_d,seg_e,seg_f,seg_g,seg_dp
        PORT Output seg_a
        PORT Output seg_b
        PORT Output seg_c
        PORT Output seg_d
        PORT Output seg_e
        PORT Output seg_f
        PORT Output seg_g
        PORT Output seg_dp
        PORT Output an(0)
        PORT Output an(1)
        PORT Output an(2)
        PORT Output an(3)
        PORT Output vga_red
        PORT Output vga_green
        PORT Output vga_blue
        PORT Output vga_hs
        PORT Output vga_vs
        PORT Input ps2c
        PORT Input clk_ic4
        PORT Input ps2d
        PORT Input btn3
        PORT Output ld(0)
        PORT Output ld(1)
        PORT Output ld(2)
        PORT Output ld(4)
        PORT Output ld(5)
        PORT Output ld(6)
        PORT Output ld(7)
        PORT Output ld(3)
        BEGIN BLOCKDEF vga_int
            TIMESTAMP 2004 9 13 18 46 48
            RECTANGLE N 64 -320 352 0 
            LINE N 64 -288 0 -288 
            RECTANGLE N 0 -60 64 -36 
            LINE N 64 -48 0 -48 
            LINE N 352 -288 416 -288 
            LINE N 352 -224 416 -224 
            LINE N 352 -160 416 -160 
            LINE N 352 -96 416 -96 
            LINE N 352 -32 416 -32 
            LINE N 64 -208 0 -208 
            LINE N 64 -128 0 -128 
        END BLOCKDEF
        BEGIN BLOCKDEF cntrl
            TIMESTAMP 2004 10 27 16 54 38
            LINE N 64 -288 0 -288 
            LINE N 64 -224 0 -224 
            LINE N 64 -160 0 -160 
            LINE N 320 -208 384 -208 
            LINE N 320 -128 384 -128 
            RECTANGLE N 320 -60 384 -36 
            LINE N 320 -48 384 -48 
            RECTANGLE N 64 -320 320 0 
            LINE N 64 -96 0 -96 
            RECTANGLE N 0 -108 64 -84 
            LINE N 64 -32 0 -32 
            RECTANGLE N 0 -44 64 -20 
        END BLOCKDEF
        BEGIN BLOCKDEF read_ps2
            TIMESTAMP 2004 10 26 14 41 2
            LINE N 64 -224 0 -224 
            LINE N 64 -160 0 -160 
            LINE N 64 -96 0 -96 
            LINE N 64 -32 0 -32 
            LINE N 320 -160 384 -160 
            LINE N 320 -96 384 -96 
            RECTANGLE N 320 -108 384 -84 
            RECTANGLE N 320 -172 384 -148 
            RECTANGLE N 64 -256 320 12 
            LINE N 320 -224 384 -224 
            RECTANGLE N 320 -44 384 -20 
            LINE N 320 -32 384 -32 
        END BLOCKDEF
        BEGIN BLOCKDEF game_title
            TIMESTAMP 2004 9 27 16 48 42
            RECTANGLE N 64 -128 320 0 
            LINE N 64 -96 0 -96 
            LINE N 320 -96 384 -96 
            RECTANGLE N 320 -108 384 -84 
            LINE N 320 -32 384 -32 
            RECTANGLE N 320 -44 384 -20 
        END BLOCKDEF
        BEGIN BLOCK read_ps2_inst read_ps2
            PIN Clk clk_ic4
            PIN PS2_Clk ps2c
            PIN PS2_Data ps2d
            PIN Reset btn3
            PIN left_dir(1:0) lf_dir(1:0)
            PIN right_dir(1:0) rt_dir(1:0)
            PIN serve serve
            PIN ps2_code(7:0) ld(7:0)
        END BLOCK
        BEGIN BLOCK cntrl_inst cntrl
            PIN CLK clk_ic4
            PIN RESET btn3
            PIN SERVE serve
            PIN HSYNCH hsync
            PIN VSYNCH vsync
            PIN COLOR(1:0) XLXN_31(1:0)
            PIN left_dir(1:0) lf_dir(1:0)
            PIN right_dir(1:0) rt_dir(1:0)
        END BLOCK
        BEGIN BLOCK vga_inst vga_int
            PIN CLK clk_ic4
            PIN COLOR(1:0) XLXN_31(1:0)
            PIN RED vga_red
            PIN BLUE vga_blue
            PIN GREEN vga_green
            PIN VSYNCH_OUT vga_vs
            PIN HSYNCH_OUT vga_hs
            PIN HSYNCH_IN hsync
            PIN VSYNCH_IN vsync
        END BLOCK
        BEGIN BLOCK title_inst game_title
            PIN clk clk_ic4
            PIN seven_seg(7:0) seg_a,seg_b,seg_c,seg_d,seg_e,seg_f,seg_g,seg_dp
            PIN an(3:0) an(3:0)
        END BLOCK
    END NETLIST
    BEGIN SHEET 1 3520 2720
        BEGIN BRANCH seg_a
            WIRE 3024 208 3104 208
            WIRE 3104 208 3184 208
            BEGIN DISPLAY 3104 208 ATTR LOC
                ALIGNMENT SOFT-BCENTER
                DISPLAYFORMAT NAMEEQUALSVALUE
            END DISPLAY
        END BRANCH
        BEGIN BRANCH seg_b
            WIRE 3024 272 3104 272
            WIRE 3104 272 3184 272
            BEGIN DISPLAY 3104 272 ATTR LOC
                ALIGNMENT SOFT-BCENTER
                DISPLAYFORMAT NAMEEQUALSVALUE
            END DISPLAY
        END BRANCH
        BEGIN BRANCH seg_c
            WIRE 3024 336 3104 336
            WIRE 3104 336 3184 336
            BEGIN DISPLAY 3104 336 ATTR LOC
                ALIGNMENT SOFT-BCENTER
                DISPLAYFORMAT NAMEEQUALSVALUE
            END DISPLAY
        END BRANCH
        BEGIN BRANCH seg_d
            WIRE 3024 400 3104 400
            WIRE 3104 400 3184 400
            BEGIN DISPLAY 3104 400 ATTR LOC
                ALIGNMENT SOFT-BCENTER
                DISPLAYFORMAT NAMEEQUALSVALUE
            END DISPLAY
        END BRANCH
        BEGIN BRANCH seg_e
            WIRE 3024 464 3104 464
            WIRE 3104 464 3184 464
            BEGIN DISPLAY 3104 464 ATTR LOC
                ALIGNMENT SOFT-BCENTER
                DISPLAYFORMAT NAMEEQUALSVALUE
            END DISPLAY
        END BRANCH
        BEGIN BRANCH seg_f
            WIRE 3024 528 3104 528
            WIRE 3104 528 3184 528
            BEGIN DISPLAY 3104 528 ATTR LOC
                ALIGNMENT SOFT-BCENTER
                DISPLAYFORMAT NAMEEQUALSVALUE
            END DISPLAY
        END BRANCH
        BEGIN BRANCH seg_g
            WIRE 3024 592 3104 592
            WIRE 3104 592 3184 592
            BEGIN DISPLAY 3104 592 ATTR LOC
                ALIGNMENT SOFT-BCENTER
                DISPLAYFORMAT NAMEEQUALSVALUE
            END DISPLAY
        END BRANCH
        BEGIN BRANCH seg_dp
            WIRE 3024 656 3104 656
            WIRE 3104 656 3184 656
            BEGIN DISPLAY 3104 656 ATTR LOC
                ALIGNMENT SOFT-BCENTER
                DISPLAYFORMAT NAMEEQUALSVALUE
            END DISPLAY
        END BRANCH
        IOMARKER 3184 208 seg_a R0 28
        IOMARKER 3184 272 seg_b R0 28
        IOMARKER 3184 336 seg_c R0 28
        IOMARKER 3184 400 seg_d R0 28
        IOMARKER 3184 464 seg_e R0 28
        IOMARKER 3184 528 seg_f R0 28
        IOMARKER 3184 592 seg_g R0 28
        IOMARKER 3184 656 seg_dp R0 28
        LINE N 2428 420 2428 684 
        LINE N 2660 420 2660 680 
        LINE N 2196 420 2196 680 
        BEGIN RECTANGLE N 2328 464 2360 544 
            FILLCOLOR 255 255 0
            FILLSTYLE Solid
        END RECTANGLE
        BEGIN RECTANGLE N 2232 464 2264 544 
            FILLCOLOR 255 255 0
            FILLSTYLE Solid
        END RECTANGLE
        BEGIN RECTANGLE N 2232 560 2264 640 
            FILLCOLOR 255 255 0
            FILLSTYLE Solid
        END RECTANGLE
        BEGIN RECTANGLE N 2328 560 2360 640 
            FILLCOLOR 255 255 0
            FILLSTYLE Solid
        END RECTANGLE
        BEGIN RECTANGLE N 2264 636 2328 664 
            FILLCOLOR 255 255 0
            FILLSTYLE Solid
        END RECTANGLE
        BEGIN RECTANGLE N 2264 540 2328 572 
            FILLCOLOR 255 255 0