music.vhd

电子琴

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- PROGRAM "Quartus II"
-- VERSION "Version 5.1 Build 176 10/26/2005 SJ Full Version"

LIBRARY ieee;
USE ieee.std_logic_1164.all; 

LIBRARY work;

ENTITY music IS 
	port
	(
		r1 :  IN  STD_LOGIC;
		r2 :  IN  STD_LOGIC;
		r3 :  IN  STD_LOGIC;
		r4 :  IN  STD_LOGIC;
		clock :  IN  STD_LOGIC;
		c1 :  OUT  STD_LOGIC;
		c2 :  OUT  STD_LOGIC;
		c3 :  OUT  STD_LOGIC;
		c4 :  OUT  STD_LOGIC;
		music :  OUT  STD_LOGIC
	);
END music;

ARCHITECTURE bdf_type OF music IS 

component \18\
	PORT(clock : IN STD_LOGIC;
		 1 : OUT STD_LOGIC;
		 8 : OUT STD_LOGIC
	);
end component;

component \29\
	PORT(clock : IN STD_LOGIC;
		 2 : OUT STD_LOGIC;
		 9 : OUT STD_LOGIC
	);
end component;

component select
	PORT(row11 : IN STD_LOGIC;
		 row22 : IN STD_LOGIC;
		 row33 : IN STD_LOGIC;
		 row44 : IN STD_LOGIC;
		 col11 : IN STD_LOGIC;
		 col22 : IN STD_LOGIC;
		 col33 : IN STD_LOGIC;
		 re : IN STD_LOGIC;
		 col44 : IN STD_LOGIC;
		 1 : IN STD_LOGIC;
		 2 : IN STD_LOGIC;
		 3 : IN STD_LOGIC;
		 4 : IN STD_LOGIC;
		 5 : IN STD_LOGIC;
		 6 : IN STD_LOGIC;
		 7 : IN STD_LOGIC;
		 8 : IN STD_LOGIC;
		 9 : IN STD_LOGIC;
		 A : IN STD_LOGIC;
		 B : IN STD_LOGIC;
		 C : IN STD_LOGIC;
		 D : IN STD_LOGIC;
		 0 : IN STD_LOGIC;
		 E : IN STD_LOGIC;
		 clock : IN STD_LOGIC;
		 f : OUT STD_LOGIC
	);
end component;

component \3a\
	PORT(clock : IN STD_LOGIC;
		 3 : OUT STD_LOGIC;
		 A : OUT STD_LOGIC
	);
end component;

component \4b\
	PORT(clock : IN STD_LOGIC;
		 4 : OUT STD_LOGIC;
		 B : OUT STD_LOGIC
	);
end component;

component \5c\
	PORT(clock : IN STD_LOGIC;
		 5 : OUT STD_LOGIC;
		 C : OUT STD_LOGIC
	);
end component;

component \6d\
	PORT(clock : IN STD_LOGIC;
		 6 : OUT STD_LOGIC;
		 D : OUT STD_LOGIC
	);
end component;

component keyboard
	PORT(clock : IN STD_LOGIC;
		 r1 : IN STD_LOGIC;
		 r2 : IN STD_LOGIC;
		 r3 : IN STD_LOGIC;
		 r4 : IN STD_LOGIC;
		 col1 : OUT STD_LOGIC;
		 col2 : OUT STD_LOGIC;
		 col3 : OUT STD_LOGIC;
		 col4 : OUT STD_LOGIC;
		 row1 : OUT STD_LOGIC;
		 row2 : OUT STD_LOGIC;
		 row3 : OUT STD_LOGIC;
		 row4 : OUT STD_LOGIC;
		 c1 : OUT STD_LOGIC;
		 c2 : OUT STD_LOGIC;
		 c3 : OUT STD_LOGIC;
		 c4 : OUT STD_LOGIC;
		 report : OUT STD_LOGIC
	);
end component;

component \07e\
	PORT(clock : IN STD_LOGIC;
		 0 : OUT STD_LOGIC;
		 7 : OUT STD_LOGIC;
		 E : OUT STD_LOGIC
	);
end component;

component \100\
	PORT(clock : IN STD_LOGIC;
		 100hz : OUT STD_LOGIC
	);
end component;

signal	SYNTHESIZED_WIRE_0 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_1 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_2 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_3 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_4 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_5 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_6 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_7 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_8 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_9 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_10 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_11 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_12 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_13 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_14 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_15 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_16 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_17 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_18 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_19 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_20 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_21 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_22 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_23 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_24 :  STD_LOGIC;


BEGIN 



b2v_inst : \18\
PORT MAP(clock => clock,
		 1 => SYNTHESIZED_WIRE_9,
		 8 => SYNTHESIZED_WIRE_16);

b2v_inst1 : \29\
PORT MAP(clock => clock,
		 2 => SYNTHESIZED_WIRE_10,
		 9 => SYNTHESIZED_WIRE_17);

b2v_inst10 : select
PORT MAP(row11 => SYNTHESIZED_WIRE_0,
		 row22 => SYNTHESIZED_WIRE_1,
		 row33 => SYNTHESIZED_WIRE_2,
		 row44 => SYNTHESIZED_WIRE_3,
		 col11 => SYNTHESIZED_WIRE_4,
		 col22 => SYNTHESIZED_WIRE_5,
		 col33 => SYNTHESIZED_WIRE_6,
		 re => SYNTHESIZED_WIRE_7,
		 col44 => SYNTHESIZED_WIRE_8,
		 1 => SYNTHESIZED_WIRE_9,
		 2 => SYNTHESIZED_WIRE_10,
		 3 => SYNTHESIZED_WIRE_11,
		 4 => SYNTHESIZED_WIRE_12,
		 5 => SYNTHESIZED_WIRE_13,
		 6 => SYNTHESIZED_WIRE_14,
		 7 => SYNTHESIZED_WIRE_15,
		 8 => SYNTHESIZED_WIRE_16,
		 9 => SYNTHESIZED_WIRE_17,
		 A => SYNTHESIZED_WIRE_18,
		 B => SYNTHESIZED_WIRE_19,
		 C => SYNTHESIZED_WIRE_20,
		 D => SYNTHESIZED_WIRE_21,
		 0 => SYNTHESIZED_WIRE_22,
		 E => SYNTHESIZED_WIRE_23,
		 clock => clock,
		 f => music);

b2v_inst2 : \3a\
PORT MAP(clock => clock,
		 3 => SYNTHESIZED_WIRE_11,
		 A => SYNTHESIZED_WIRE_18);

b2v_inst3 : \4b\
PORT MAP(clock => clock,
		 4 => SYNTHESIZED_WIRE_12,
		 B => SYNTHESIZED_WIRE_19);

b2v_inst4 : \5c\
PORT MAP(clock => clock,
		 5 => SYNTHESIZED_WIRE_13,
		 C => SYNTHESIZED_WIRE_20);

b2v_inst5 : \6d\
PORT MAP(clock => clock,
		 6 => SYNTHESIZED_WIRE_14,
		 D => SYNTHESIZED_WIRE_21);

b2v_inst6 : keyboard
PORT MAP(clock => SYNTHESIZED_WIRE_24,
		 r1 => r1,
		 r2 => r2,
		 r3 => r3,
		 r4 => r4,
		 col1 => SYNTHESIZED_WIRE_4,
		 col2 => SYNTHESIZED_WIRE_5,
		 col3 => SYNTHESIZED_WIRE_6,
		 col4 => SYNTHESIZED_WIRE_8,
		 row1 => SYNTHESIZED_WIRE_0,
		 row2 => SYNTHESIZED_WIRE_1,
		 row3 => SYNTHESIZED_WIRE_2,
		 row4 => SYNTHESIZED_WIRE_3,
		 c1 => c1,
		 c2 => c2,
		 c3 => c3,
		 c4 => c4,
		 report => SYNTHESIZED_WIRE_7);

b2v_inst7 : \07e\
PORT MAP(clock => clock,
		 0 => SYNTHESIZED_WIRE_22,
		 7 => SYNTHESIZED_WIRE_15,
		 E => SYNTHESIZED_WIRE_23);

b2v_inst8 : \100\
PORT MAP(clock => clock,
		 100hz => SYNTHESIZED_WIRE_24);

END;