sysdot11end.c

PNE 3.3 wlan source code, running at more than vxworks6.x version

        /* Set the delay factor to be 0 */
        0
    },

    /* This structure is used to add CPU based configuration to allow
    access from the CPU to the bus device and the bus device to DMA 
    into system memory etc... */ 
    {
        /* Dma mapping, and BSP level bus translation is
        required by this BSP */
        DOT11_BSP_FUNC_NOT_SUPPORTED, 
        DOT11_BSP_FUNC_NOT_SUPPORTED, 
        DOT11_BSP_FUNC_NOT_SUPPORTED, 
        DOT11_BSP_FUNC_NOT_SUPPORTED,
        /* Bus address into a cpu address conversion offset */
        PCI2CPU_MEM_OFFSET, 
        /* Use a hardcoded interrupt vector */
        DOT11_BSP_PARAM_NOT_SUPPORTED, 
        /* This BSP makes use of the cache driver */
        TRUE,
        /* Used by the BSP level int connect/disconnect routine */
        DOT11_BSP_PARAM_NOT_SUPPORTED,
        /* System mmu mapping mask */
        DOT11_BSP_PARAM_NOT_SUPPORTED,
        /* System mmu mapping configuration */
        DOT11_BSP_PARAM_NOT_SUPPORTED,
        /* interrupt level to interrupt vector translation */
        0,
        /* Bus master aliasing */
        PCI2DRAM_BASE_ADRS
    },
     
    /* This structure provides system level functions */
    {
        /* Number of bus slots on the board */
        BUS_SLOTS_3,  
        /* This BSP has a rotuine to add devs to the end table 
        dynamically */
        DOT11_BSP_FUNC_NOT_SUPPORTED        
    }
#elif defined(__INCwrSbcPowerQuiccIIh)
    /* Current BSP ID field */
    IS_POWERQUICC_II,

    /* The following structure defines functions that are needed
    to set up the device on the bus. Typically these calls are provided
    by the BSP layer or standard vxWorks pciLib */
    {
        /* Use standard pciLib device probing routines */
        pciFindDevice, 
        /* Use standard pciLib int connect routines */
        pciDeviceIntConnect, 
        /* Use standard pciLib int disconnect routines */
        pciDeviceIntDisconnect, 
        /* Use BSP defined int enable/disable routines - see sysLib.c
        for details */
        pciDeviceIntEnable,                
        pciDeviceIntDisable,  
        /* Use BSP defined hardware based delay routines - see sysLib.c
        for details */
        sysUsDelay,
        /* Bus configuration access is ok by default */
        DOT11_BSP_FUNC_NOT_SUPPORTED, 
        DOT11_BSP_FUNC_NOT_SUPPORTED,
        /* Assign bus resources to the bus controller */
        DOT11_BSP_FUNC_NOT_SUPPORTED,
        /* Set the delay factor to be 0 */
        0
    },

    /* This structure is used to add CPU based configuration to allow
    access from the CPU to the bus device and the bus device to DMA 
    into system memory etc... */ 
    {
        /* Dma mapping, mmu mapping and BSP level bus translation is
        not required by this BSP */
        DOT11_BSP_FUNC_NOT_SUPPORTED, 
        DOT11_BSP_FUNC_NOT_SUPPORTED, 
        DOT11_BSP_FUNC_NOT_SUPPORTED, 
        DOT11_BSP_FUNC_NOT_SUPPORTED,
        /* Bus address into a cpu address conversion offset */
        0, 
        /* Nothing special about the interrupt vector or levels */
        DOT11_BSP_PARAM_NOT_SUPPORTED, 
        /* This BSP makes use of the cache driver */
        TRUE,
        /* Used by the BSP level int connect/disconnect routine */
        DOT11_BSP_PARAM_NOT_SUPPORTED,
        /* System mmu mapping mask */
        DOT11_BSP_PARAM_NOT_SUPPORTED,
        /* System mmu mapping configuration */
        DOT11_BSP_PARAM_NOT_SUPPORTED,
        /* interrupt level to interrupt vector translation */
        0,
        /* Bus master aliasing */
        DOT11_BSP_PARAM_NOT_SUPPORTED
    },
     
    /* This structure provides system level functions */
    {
        /* Number of bus slots on the board */
        BUS_SLOTS_1,  
        /* There is no routine to add devs to the end table dynamically
        in this BSP */
        DOT11_BSP_FUNC_NOT_SUPPORTED        
    }
#elif defined(INCwrSbc85xxh)
    /* Current BSP ID field */
    IS_POWERQUICC_III,

    /* The following structure defines functions that are needed
    to set up the device on the bus. Typically these calls are provided
    by the BSP layer or standard vxWorks pciLib */
    {
        /* Use standard pciLib device probing routines */
        pciFindDevice, 
        /* Use standard pciLib int connect routines */
        pciIntConnect, 
        /* Use standard pciLib int disconnect routines */
        pciIntDisconnect, 
        /* Use BSP defined int enable/disable routines - see sysLib.c
        for details */
        intEnable,                
        intDisable,  
        /* Use BSP defined hardware based delay routines - see sysLib.c
        for details */
        sysUsDelay,
        /* Bus configuration access is ok by default */
        DOT11_BSP_FUNC_NOT_SUPPORTED, 
        DOT11_BSP_FUNC_NOT_SUPPORTED,
        /* Assign bus resources to the bus controller */
        DOT11_BSP_FUNC_NOT_SUPPORTED,
        /* Set the delay factor to be 0 */
        0
    },

    /* This structure is used to add CPU based configuration to allow
    access from the CPU to the bus device and the bus device to DMA 
    into system memory etc... */ 
    {
        /* Dma mapping, mmu mapping and BSP level bus translation is
        not required by this BSP */
        DOT11_BSP_FUNC_NOT_SUPPORTED, 
        DOT11_BSP_FUNC_NOT_SUPPORTED, 
        DOT11_BSP_FUNC_NOT_SUPPORTED, 
        DOT11_BSP_FUNC_NOT_SUPPORTED,
        /* Bus address into a cpu address conversion offset */
        0, 
        /* Nothing special about the interrupt vector or levels */
        DOT11_BSP_PARAM_NOT_SUPPORTED, 
        /* This BSP makes use of the cache driver */
        TRUE,
        /* Used by the BSP level int connect/disconnect routine */
        DOT11_BSP_PARAM_NOT_SUPPORTED,
        /* System mmu mapping mask */
        DOT11_BSP_PARAM_NOT_SUPPORTED,
        /* System mmu mapping configuration */
        DOT11_BSP_PARAM_NOT_SUPPORTED,
        /* interrupt level to interrupt vector translation */
        0,
        /* Bus master aliasing */
        DOT11_BSP_PARAM_NOT_SUPPORTED
    },
     
    /* This structure provides system level functions */
    {
        /* Number of bus slots on the board */
        BUS_SLOTS_4,  
        /* There is no routine to add devs to the end table dynamically
        in this BSP */
        DOT11_BSP_FUNC_NOT_SUPPORTED        
    }
#elif defined(INCIceCube5200h)
    /* Current BSP ID field */
    IS_ICECUBE5200,

    /* The following structure defines functions that are needed
    to set up the device on the bus. Typically these calls are provided
    by the BSP layer or standard vxWorks pciLib */
    {
        /* Use standard pciLib device probing routines */
        pciFindDevice, 
        /* Use standard pciLib int connect routines */
        intConnect, 
        /* Use standard pciLib int disconnect routines */
        DOT11_BSP_FUNC_NOT_SUPPORTED, 
        /* Use BSP defined int enable/disable routines - see sysLib.c
        for details */
        intEnable,                
        intDisable,  
        /* Use BSP defined hardware based delay routines - see sysLib.c
        for details */
        sysMsDelay,
        /* Bus configuration access is ok by default */
        DOT11_BSP_FUNC_NOT_SUPPORTED, 
        DOT11_BSP_FUNC_NOT_SUPPORTED,
        /* Assign bus resources to the bus controller */
        DOT11_BSP_FUNC_NOT_SUPPORTED,
        /* Set the delay factor to be 0 */
        10
    },

    /* This structure is used to add CPU based configuration to allow
    access from the CPU to the bus device and the bus device to DMA 
    into system memory etc... */ 
    {
        /* Dma mapping, mmu mapping and BSP level bus translation is
        not required by this BSP */
        DOT11_BSP_FUNC_NOT_SUPPORTED, 
        DOT11_BSP_FUNC_NOT_SUPPORTED, 
        DOT11_BSP_FUNC_NOT_SUPPORTED, 
        DOT11_BSP_FUNC_NOT_SUPPORTED,
        /* Bus address into a cpu address conversion offset */
        0, 
        /* Nothing special about the interrupt vector or levels */
        DOT11_BSP_PARAM_NOT_SUPPORTED, 
        /* This BSP makes use of the cache driver */
        TRUE,
        /* Used by the BSP level int connect/disconnect routine */
        DOT11_BSP_PARAM_NOT_SUPPORTED,
        /* System mmu mapping mask */
        DOT11_BSP_PARAM_NOT_SUPPORTED,
        /* System mmu mapping configuration */
        DOT11_BSP_PARAM_NOT_SUPPORTED,
        /* interrupt level to interrupt vector translation */
        0,
        /* Bus master aliasing */
        DOT11_BSP_PARAM_NOT_SUPPORTED
    },
     
    /* This structure provides system level functions */
    {
        /* Number of bus slots on the board */
        BUS_SLOTS_1,  
        /* There is no routine to add devs to the end table dynamically
        in this BSP */
        DOT11_BSP_FUNC_NOT_SUPPORTED        
    }
#elif defined(INCLite5200h)
    /* Current BSP ID field */
    IS_ICECUBE5200,

    /* The following structure defines functions that are needed
    to set up the device on the bus. Typically these calls are provided
    by the BSP layer or standard vxWorks pciLib */
    {
        /* Use standard pciLib device probing routines */
        pciFindDevice, 
        /* Use standard pciLib int connect routines */
        intConnect, 
        /* Use standard pciLib int disconnect routines */
        DOT11_BSP_FUNC_NOT_SUPPORTED, 
        /* Use BSP defined int enable/disable routines - see sysLib.c
        for details */
        intEnable,                
        intDisable,  
        /* Use BSP defined hardware based delay routines - see sysLib.c
        for details */
        sysMsDelay,
        /* Bus configuration access is ok by default */
        DOT11_BSP_FUNC_NOT_SUPPORTED, 
        DOT11_BSP_FUNC_NOT_SUPPORTED,
        /* Assign bus resources to the bus controller */
        DOT11_BSP_FUNC_NOT_SUPPORTED,
        /* Set the delay factor to be 0 */
        10
    },

    /* This structure is used to add CPU based configuration to allow
    access from the CPU to the bus device and the bus device to DMA 
    into system memory etc... */ 
    {
        /* Dma mapping, mmu mapping and BSP level bus translation is
        not required by this BSP */
        DOT11_BSP_FUNC_NOT_SUPPORTED, 
        DOT11_BSP_FUNC_NOT_SUPPORTED, 
        DOT11_BSP_FUNC_NOT_SUPPORTED, 
        DOT11_BSP_FUNC_NOT_SUPPORTED,
        /* Bus address into a cpu address conversion offset */
        0x0,
        /* Nothing special about the interrupt vector or levels */
        DOT11_BSP_PARAM_NOT_SUPPORTED, 
        /* This BSP makes use of the cache driver */
        TRUE,
        /* Used by the BSP level int connect/disconnect routine */
        DOT11_BSP_PARAM_NOT_SUPPORTED,
        /* System mmu mapping mask */
        DOT11_BSP_PARAM_NOT_SUPPORTED,
        /* System mmu mapping configuration */
        DOT11_BSP_PARAM_NOT_SUPPORTED,
        /* interrupt level to interrupt vector translation */
        0,
        /* Bus master aliasing */
        BUS_PCI_SLV_MEM_LOCAL_B
    },
     
    /* This structure provides system level functions */
    {
        /* Number of bus slots on the board */
        BUS_SLOTS_1,  
        /* There is no routine to add devs to the end table dynamically
        in this BSP */
        DOT11_BSP_FUNC_NOT_SUPPORTED        
    }
#else
#error "Unsupported CPU family - See Porting Guide"
#endif
    };


/* Local defines */
#define SYS_DOT11_BUS_TO_MSTR(p, addr) \
addr |= p->bsp->cpu.memAlias;
#define SYS_DOT11_MSTR_TO_BUS(p, addr) \
addr &= ~p->bsp->cpu.memAlias;
#define SYS_DOT11_ILEVEL(p, level) \
level -= p->bsp->cpu.intLvlFactor;
#define SYS_DOT11_CPU_TO_PCI_ADDR(p, baseAddr) \
baseAddr+=p->cpu.memAddrOffset;
#define SYS_DOT11_ILEVEL_TO_IVEC(p, level, vector) \
vector = level + p->cpu.lvlToVec;

/* Local bsp binding structure */
static DOT11_BSP  config;
static DOT11_BSP* binding = NULL;

/********************************************************************
* sysDot11BusInit - bus initialization for dot11 devices
*
* This routine creates 2 bindings one of which is a binding to the
* BSP structure, while the other is binding to local support 
* functions that are used by the higher layers of the device driver. 
* The BSP level binding structure contains references to the 
* required low level functions that are needed to allow the device 
* driver accesses the physical device (e.g. ar5211 pci card), while 
* the support function binding binds the current layer to the upper
* layers of the device driver. 
* The next stage of initialization performed is creating a device
* resource table for all of the supported devices on the bus.
*
* RETURNS: None 
*
* NOMANUAL
*/
void sysDot11BusInit(void)
    {
    UINT32 unit;

    /* Bind the driver to the bsp layer */
    binding = &config;

    /* Install the required higher level support functions */
    binding->support.sysIntConnect = sysDot11IntConnect;
    binding->support.sysIntDisconnect = sysDot11IntDisconnect;
    binding->support.sysIntEnable = sysDot11IntEnable;
    binding->support.sysIntDisable = sysDot11IntDisable;