sysdot11end.c

PNE 3.3 wlan source code, running at more than vxworks6.x version

/* sysDot11End.c - system configuration module for END device */
 
/* Copyright 2001-2004 Wind River Systems, Inc. */

/*
modification history
-------------------
01f,19oct05,rb  Added support for lite5200 BSP
01e,09sep05,rb  Added countryCode as boot parameter
01d,25jul05,eja  Add delay factor for standard iceCube5200 sysMsDelay function
01c,18jul05,eja  Add support for icecube BSP
01b,28jun05,rb  Fix for SPR 110200 - Can't use PSK(bin) with command line
                 build
01a,08jun05,eja  Fix for B0521 - warnings
01j,26may05, rb Fix for bug B0429 - Wireless image reboots immediately after 
                loading
02i,25may05,eja Fix SH data abort under base6
02h,05may05,rb  Fix for bug B0307 - MIPs STA takes a long time to associate
02g,05may04,rb  Fix for bug B0308 - ixdp425 freezes after initing wireless
02f,25jan05,rb  Made security components optionally buildable
02e,07jan05,rb  Added members for 802.1X Integration
02d,06jan05,eja Implement support for 802.1X port authentication checking
02c,01nov04,rb  Added settings for security policies
02b,24aug04,rb  Fixed warning
02a,23aug04,rb  Wind River Wireless Ethernet Driver 2.0 FCS0
*/

/* 
* DESCRIPTION
* 
* This is the WRS-supplied configuration module for the VxWorks Atheros 
* 521x END driver. 
*
* This file implements generic binding layers between the 
* high level device driver and the supported low level board support packages 
* (BPSs). Currently the following BSPs are supported by this module 
*
* 1) pcPentium3                  - x86 based system. 
* 2) ixdp425                     - XSCALE based system.
* 3) wrPpmcIdt334_mips32sfIDT334 - MIPS based system. 
* 4) ms7751se_le                 - SH7750 based system. 
* 5) malta4kc_mips32sf           - MIPS based system. 
* 6) integrator720t              - ARM720T based system.
* 7) wrSbcPowerQuiccII           - PPC POWERQUICCII system.
* 8) wrSbc8560                   - PPC POWERQUICIII system.
* 9) malta5261_mips64            - MIPS based system. 
* 10) ms7751rse_le               - SH7750 based system. 
* 11) icecube5200                - PPC5200 based system. 
*
* It is the aim of this file to provide a flexible and portable mechanism
* by which a user can provide support for a new BSP other than the three
* currently supported versions.
*
* The Athreos chip sets which are supprted by the device driver layer are
* all PCI based so in order to support Card Bus which is a PCI variant in the
* future the naming convention for functions in this module uses the 
* term "bus" as a descriptor rather than "pci". This purely a naming 
* convertion as all of the currently supported cards are PCI based.
*
* This module works as a generic mechanism for connecting the device
* driver to the BSP supported bus hardware. Since any given BSP may have
* differing hardware implementations for the PCI bus this module has 
* accounted for the changes on 3 differing architectures. The x86 based
* variant has a BIOS which will instanciate the bus on system boot up
* thus making the task of getting card information rather easy. The MIPS
* and XSCALE variants on the other hand are BIOSless systems but do 
* provide the hooks so that the BSP can peform a bus mapping much like 
* the x86 provided the BSP boot code makes an explicit call the function
* which performs the mapping.
*
* Once the bus mapping has been performed (i.e. All cards in the PCI slots
* have been assigned a valid bus level memory region), information for 
* each valid card must be extracted and saved for each Atheros card in the
* system.
* 
* Typical values that are set up by the card intansiation process are
* assigning a memory window in the bus addressible memory region, 
* assigning an interrupt level and interrupt vector for the slot,
* as well as assigning a memory mapped base address so that the cards
* registers can be accessed. 
* 
* Most of the functions in this file are wrapper functions that contain
* a binding to the BSP layer. The wrapper functions are bound to the 
* device driver layer while the BSP level function are bound to low level
* BSP specific calls (e.g. pciIntConnect()). By emplying this method 
* the device driver does not have to worry about how the BSP level call
* is implemeted. The implementation is handled by the BSP and accessed 
* through the BSP binding layer. 
* 
* When extending this file for use with a new BSP the user should pay
* attention to the following:
*
* 1) Add the new CPU type to the BSP_T enumeration found in 
*    sysDot11End.h 
* 2) Fill in the entries for the BSP binding into boardSupport 
*    structure. Currently the entry contains NULL and 0'ed entries
*    and issues a compile time error stating that the current BSP
*    type is not supported. NOTE: Do not confuse the BSP_T 
*    enumeration with the CPU define. The CPU define is defined at
*    compile time through the system build environment. The CPU 
*    macro is used at compile time to implement the proper BSP 
*    level binding configuration while the BSP_T is typically
*    used to handle the nuances found on a per BSP case. See code
*    base for examples.
* 3) The following forms a basis for the most common BSP layer
*    functions that need to get bound to the BSP binding based on
*    the following structure (see sysDot11End.h for details):
*    - type is the bsp type.
*    - bus.fndDevice is the BSP level bus probing binding. 
*    - bus.intConnect is the bus level interrupt connection binding.
*    - bus.intDisconnect is the bus level interrupt disconnection binding. 
*    - bus.intEnable is the bus level interrupt enable binding.
*    - bus.intEnable is the bus level interrupt disable binding.
*    - bus.usDelay is the BSP level usecond delay binding.
*    - bus.errDisable is the BSP level bus error disable binding. See NOTE(1).
*    - bus.errEnable is the BSP level bus error enable binding. See NOTE(1).
*    - bus.delayFactor is used for invalid usec delay functions.
*    - cpu.busToVirt is a CPU level binding that peforms bus to virtual
*      address translation.
*    - cpu.virtToBus is a CPU level binding that peforms virtual to bus
*      address translation.
*    - cpu.dmaMappingAdd is the CPU level DMA memory mapping binding.
*    - cpu.mmuMappingAdd is the CPU level pci memory space MMU mapping 
*      binding. See NOTE(2).
*    - cpu.iVec is the hardware binding to maintain a list of 
*      hard coded interrupt vectors that are used for multiple card
*      support. See NOTE(1).
*    - cpu.inumTbl is a CPU level interrupt vector to interrupt number 
*      conversion table. See NOTE(2).
*    - cpu.useCacheDrv is a flag that indicates whether or not to use
*      the standard cache libraries.
*    - cpu.intLvlFactor Compensates for interrupt level translation in the
*      intEnable function.
*    - cpu.mmuMask is used by systems that peform dynamic bus mappings of 
*      there address space.
*    - cpu.mmuConfig is used by systems that peform dynamic bus mappings of 
*      there address space.
*    - cpu.lvlToVec is used to translate interrupt level to interrupt 
*      vectors in systems that require it.
*    - system.busSlots defines the number of bus slots on the board.
*    - system.endDevTblAdd is used to add a new end device if the system 
*      supports the functionality.
*
* NOTE(1): These functions and/or parameters are only required by the 
*          wrPpmcIdt334_mips32sfIDT334 BSP.
* NOTE(2): These functions and/or parameters are only required by the 
*          pcPentium3.
*
* As it can be shown from above many but not all of the bindings are 
* required by the supported BSPs. The current binding structure may
* need to be extended to support new BSPs in the future.
*/ 

#include "wlan/bsp/sysDot11End.h"


#define SYS_DOT11_DELAY() \
{ \
volatile UINT32 temp = 0xFFFFFFFF; \
int idx; \
for(idx = 0; idx < 0x0000FFF; idx++) \
{ \
 temp ^= 0xFFFFFFFF; \
} \
}

/* GLOBAL FUNCTIONS  */

/* Load an instance of the DOT11 END driver */
END_OBJ* sysDot11EndLoad
    (
    char* initString, /* Initial parameters to initialize device with */
    void* pBsp        /* unused */
    ); 

/* Bus initialization for DOT11 devices */
void sysDot11BusInit(void);

/* LOCAL FUNCTIONS */

/* Bus initialization for DOT11 devices */
LOCAL void sysDot11Init(void);

/* Bind an END device into the end table */
LOCAL STATUS sysDot11EndTblBind    
    (
    INT32 devNum /* Device instance number */
    );

/* Performs bus to virtual address transaltion */
LOCAL UINT32 sysDot11BusToVirt
    (
    UINT32 busAddr /* Physical address */
    );

/* Performs virtual to physical address transaltion */
LOCAL UINT32 sysDot11VirtToBus
    (
    UINT32 virtAddr /* Virtual address */
    );

/* Invalidate the system cache */
LOCAL STATUS sysDot11CacheInvalidate
    (
    void*  addr,  /* Start address of the cache */
    UINT32 nBytes /* Number of bytes to flush */
    );

/* Flush the system cache */
LOCAL STATUS sysDot11CacheFlush
    (
    void*  addr,  /* Start address of the cache */
    UINT32 nBytes /* Number of bytes to flush */
    );

/* Flush the system write buffer */
LOCAL STATUS sysDot11WbufFlush(void);

/* Free up allocated driver memory */
LOCAL void sysDot11DmaMemFree(UINT32 devNum);

/* Enable the system level interrupt */
LOCAL void sysDot11IntConnect
    (
    INT32   vector,    /* interrupt vector */ 
    INT32   routine,   /* interrupt service routine */
    INT32   parameter, /* parameter used by the isr */
    STATUS* result     /* result of api call */
    );

/* Disable the system level interrupt */
LOCAL void sysDot11IntDisconnect
    (
    INT32   vector,    /* interrupt vector */ 
    INT32   routine,   /* interrupt service routine */
    INT32   parameter, /* parameter used by the isr */
    STATUS* result     /* result of api call */
    );

/* Enable the board level interrupt */
LOCAL void sysDot11IntEnable
    (
    INT32   intLevel,  /* interrupt request level */
    STATUS* result     /* result of API call */
    );

/* Disable the board level interrupt */
LOCAL void sysDot11IntDisable
    (
    INT32   intLevel,  /* interrupt request level */
    STATUS* result     /* result of API call */
    );

/* System delay in the unit of micro second */
LOCAL void sysDot11UsDelay 
    (
    INT32 uSec /* Micro second delay */
    );

/* Detect the DOT11 devices on the bus */
LOCAL STATUS sysDot11DeviceFind 
    (
    UINT32  vendorId, /* Vendor ID */
    UINT32  deviceId, /* Device ID */
    INT32   instance, /* Device instance */
    UINT32* pciBus,   /* Bus number */
    UINT32* pciDev,   /* Bus device */
    UINT32* pciFunc   /* Bus function */
    );

/* Detect the DOT11 devices on the bus */
LOCAL STATUS sysDot11DeviceFind2 
    (
    UINT32  vendorId, /* Vendor ID */
    UINT32  deviceId, /* Device ID */
    INT32   instance, /* Device instance */
    UINT32* pciBus,   /* Bus number */
    UINT32* pciDev,   /* Bus device */
    UINT32* pciFunc   /* Bus function */
    );

/* Update a resource configuration structure */ 
LOCAL STATUS sysDot11BusConfig
    (
    DOT11_BUS_RSRC*    resource, /* resource binding */
    DOT11_BSP_BINDING* bsp       /* bsp level binding */
    );

/* BSP CONFIGURATION PARAMETERS */

/* Default WLAN configuration parameters */
static DOT11_DEFAULT_CONFIG sysDot11WlanCfg =
    {
    /* Network Name (also called the SSID, BSS Name or ESS Name) */
    DOT11_DEFAULT_SSID,
    /* Wireless Mode - STA, IBSS or AP mode */
    DOT11_DEFAULT_MODE,
    /* Radio Type - 802.11a, 802.11b, 802.11g or other modes */
    DOT11_DEFAULT_RADIO,
    /* Default Channel - used for IBSS and AP modes only */
    DOT11_DEFAULT_CHANNEL,
    /* Default Country - used for IBSS and AP modes only */
    DOT11_DEFAULT_COUNTRY,    
    0,
    0,
    0,
    DOT11_AUTH_PSK_KEY
    };

/* Supported cards identifers */
static DOT11_BOARD_ID sysDot11Ids[] =
    {
    {
    AR5211_VENDOR_ID, /* Vendor ID */ 
    AR5211_DEVID, /* Device ID */
    0 /* Instance number for multi card support */
    },
    {
    AR5212_VENDOR_ID, /* Vendor ID */
    AR5212_DEVID, /* Device ID */
    0 /* Instance number for multi card support */
    }
    };

/* Bind the hardware specific methods that are required by one of 
the three supported BSPs into the generic binding structure */
static DOT11_BSP_BINDING hardware =
    {
#if defined(__INCmaltah)
    /* Current BSP ID field */
    IS_MALTA4KC,

#  if (defined(_WRS_VXWORKS_MAJOR) && (_WRS_VXWORKS_MAJOR == 6)) 
    /* The following structure defines functions that are needed
    to set up the device on the bus. Typically these calls are provided
    by the BSP layer or standard vxWorks pciLib */
    {
        /* Use standard pciLib device probing routines */
        pciFindDevice, 
        /* Use standard pciLib int connect routines */
        pciIntConnect, 
        /* Use standard pciLib int disconnect routines */
        pciIntDisconnect2, 
        /* Use BSP defined int enable/disable routines - see sysLib.c
        for details */
        sysIntEnablePIC,                
        sysIntDisablePIC,  
        /* Use BSP defined hardware based delay routines - see sysLib.c
        for details */
        sysUSecDelay,
        /* Bus configuration access is ok by default */
        DOT11_BSP_FUNC_NOT_SUPPORTED, 
        DOT11_BSP_FUNC_NOT_SUPPORTED,
        /* Assign bus resources to the bus controller */
        DOT11_BSP_FUNC_NOT_SUPPORTED,
        /* Set the delay factor to be 0 */