ddsa.fit.rpt

基于ALTERA CYCLONE 系列的音乐播放示例实验教程.

+--------------------------------------------------------------------------+
; LAB Logic Elements                                                       ;
+--------------------------------------------+-----------------------------+
; Number of Logic Elements  (Average = 5.25) ; Number of LABs  (Total = 4) ;
+--------------------------------------------+-----------------------------+
; 1                                          ; 1                           ;
; 2                                          ; 0                           ;
; 3                                          ; 0                           ;
; 4                                          ; 0                           ;
; 5                                          ; 1                           ;
; 6                                          ; 1                           ;
; 7                                          ; 0                           ;
; 8                                          ; 0                           ;
; 9                                          ; 1                           ;
; 10                                         ; 0                           ;
+--------------------------------------------+-----------------------------+


+------------------------------------------------------------------+
; LAB-wide Signals                                                 ;
+------------------------------------+-----------------------------+
; LAB-wide Signals  (Average = 1.25) ; Number of LABs  (Total = 4) ;
+------------------------------------+-----------------------------+
; 1 Clock                            ; 4                           ;
; 1 Sync. load                       ; 1                           ;
+------------------------------------+-----------------------------+


+---------------------------------------------------------------------------+
; LAB Signals Sourced                                                       ;
+---------------------------------------------+-----------------------------+
; Number of Signals Sourced  (Average = 5.50) ; Number of LABs  (Total = 4) ;
+---------------------------------------------+-----------------------------+
; 0                                           ; 0                           ;
; 1                                           ; 1                           ;
; 2                                           ; 0                           ;
; 3                                           ; 0                           ;
; 4                                           ; 0                           ;
; 5                                           ; 1                           ;
; 6                                           ; 1                           ;
; 7                                           ; 0                           ;
; 8                                           ; 0                           ;
; 9                                           ; 0                           ;
; 10                                          ; 1                           ;
+---------------------------------------------+-----------------------------+


+-------------------------------------------------------------------------------+
; LAB Signals Sourced Out                                                       ;
+-------------------------------------------------+-----------------------------+
; Number of Signals Sourced Out  (Average = 1.50) ; Number of LABs  (Total = 4) ;
+-------------------------------------------------+-----------------------------+
; 0                                               ; 0                           ;
; 1                                               ; 2                           ;
; 2                                               ; 2                           ;
+-------------------------------------------------+-----------------------------+


+---------------------------------------------------------------------------+
; LAB Distinct Inputs                                                       ;
+---------------------------------------------+-----------------------------+
; Number of Distinct Inputs  (Average = 4.75) ; Number of LABs  (Total = 4) ;
+---------------------------------------------+-----------------------------+
; 0                                           ; 0                           ;
; 1                                           ; 2                           ;
; 2                                           ; 0                           ;
; 3                                           ; 0                           ;
; 4                                           ; 0                           ;
; 5                                           ; 0                           ;
; 6                                           ; 0                           ;
; 7                                           ; 1                           ;
; 8                                           ; 0                           ;
; 9                                           ; 0                           ;
; 10                                          ; 1                           ;
+---------------------------------------------+-----------------------------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
    Info: Processing started: Sun Dec 12 12:02:26 2004
Info: Command: quartus_fit --import_settings_files=off --export_settings_files=off ddsa -c ddsa
Info: Automatically selected device EP1C3T100C6 for design ddsa
Info: Fitter is performing an Auto Fit compilation -- Fitter effort may be decreased to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. 
Info: No exact pin location assignment(s) for 13 pins of 13 total pins
    Info: Pin SpkS not assigned to an exact location on the device
    Info: Pin Tone[0] not assigned to an exact location on the device
    Info: Pin Tone[1] not assigned to an exact location on the device
    Info: Pin Tone[2] not assigned to an exact location on the device
    Info: Pin Tone[3] not assigned to an exact location on the device
    Info: Pin Tone[4] not assigned to an exact location on the device
    Info: Pin Tone[5] not assigned to an exact location on the device
    Info: Pin Tone[6] not assigned to an exact location on the device
    Info: Pin Tone[7] not assigned to an exact location on the device
    Info: Pin Tone[9] not assigned to an exact location on the device
    Info: Pin Tone[10] not assigned to an exact location on the device
    Info: Pin Tone[8] not assigned to an exact location on the device
    Info: Pin clk not assigned to an exact location on the device
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
    Info: Assuming a global fmax requirement of 1 MHz
    Info: Not setting a global tsu requirement
    Info: Not setting a global tco requirement
    Info: Not setting a global tpd requirement
Info: Performing register packing on registers with non-logic cell location assignments
Info: Completed register packing on registers with non-logic cell location assignments
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal clk to use Global clock in PIN 10
Info: Automatically promoted signal PreCLK~15 to use Global clock
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Started Fast Input/Output/OE register processing
Info: Finished Fast Input/Output/OE register processing
Info: Start DSP scan-chain inferencing
Info: Completed DSP scan-chain inferencing
Info: Moving registers into I/Os, LUTs, DSP and RAM blocks to improve timing and density
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Finished moving registers into I/Os, LUTs, DSP and RAM blocks
Info: Finished register packing
Info: Statistics of I/O pins that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 12 (unused VREF, 3.30 VCCIO, 11 input, 1 output, 0 bidirectional)
        Info: I/O standards used: LVTTL.
Info: Details of I/O bank before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 3 total pin(s) used --  11 pins available
        Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  17 pins available
        Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  16 pins available
        Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  17 pins available
Info: Details of I/O bank after I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has 3.30V VCCIO pins. 4 total pin(s) used --  10 pins available
        Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  17 pins available
        Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 11 total pin(s) used --  5 pins available
        Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  17 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time = 0 seconds
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Estimated most critical path is register to register delay of 3.175 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X26_Y9; Fanout = 3; REG Node = 'lpm_counter:\GenSpkS:Count11[0]_rtl_0|cntr_7t7:auto_generated|safe_q[4]'
    Info: 2: + IC(0.557 ns) + CELL(0.454 ns) = 1.011 ns; Loc. = LAB_X26_Y8; Fanout = 2; COMB Node = 'reduce_nor~69'
    Info: 3: + IC(0.105 ns) + CELL(0.340 ns) = 1.456 ns; Loc. = LAB_X26_Y8; Fanout = 11; COMB Node = 'reduce_nor~71'
    Info: 4: + IC(0.776 ns) + CELL(0.943 ns) = 3.175 ns; Loc. = LAB_X26_Y9; Fanout = 4; REG Node = 'lpm_counter:\GenSpkS:Count11[0]_rtl_0|cntr_7t7:auto_generated|safe_q[0]'
    Info: Total cell delay = 1.737 ns ( 54.71 % )
    Info: Total interconnect delay = 1.438 ns ( 45.29 % )
Info: Estimated interconnect usage is 1% of the available device resources
Info: Fitter placement operations ending: elapsed time = 0 seconds
Info: Fitter routing operations beginning
Info: Fitter routing operations ending: elapsed time = 0 seconds
Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
Info: Completed Fixed Delay Chain Operation
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Completed Auto Delay Chain Operation
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
    Info: Processing ended: Sun Dec 12 12:02:29 2004
    Info: Elapsed time: 00:00:03