📄 ddsa.fit.rpt
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; SSTL-2 Class I ; 30 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ;
; SSTL-2 Class II ; 30 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ;
; Differential SSTL-2 ; 30 pF ; (See SSTL-2) ;
+---------------------+-------+------------------------------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Resource Utilization by Entity ;
+---------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+----------------------------------------------------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+---------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+----------------------------------------------------------------------+
; |ddsa ; 21 (6) ; 17 ; 0 ; 13 ; 0 ; 4 (4) ; 1 (1) ; 16 (1) ; 15 (0) ; |ddsa ;
; |lpm_counter:\DivideCLK:Count4[0]_rtl_1| ; 4 (0) ; 4 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 4 (0) ; 4 (0) ; |ddsa|lpm_counter:\DivideCLK:Count4[0]_rtl_1 ;
; |cntr_ea7:auto_generated| ; 4 (4) ; 4 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 4 (4) ; 4 (4) ; |ddsa|lpm_counter:\DivideCLK:Count4[0]_rtl_1|cntr_ea7:auto_generated ;
; |lpm_counter:\GenSpkS:Count11[0]_rtl_0| ; 11 (0) ; 11 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 11 (0) ; 11 (0) ; |ddsa|lpm_counter:\GenSpkS:Count11[0]_rtl_0 ;
; |cntr_7t7:auto_generated| ; 11 (11) ; 11 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 11 (11) ; 11 (11) ; |ddsa|lpm_counter:\GenSpkS:Count11[0]_rtl_0|cntr_7t7:auto_generated ;
+---------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+----------------------------------------------------------------------+
+-----------------------------------------------------------------------------------+
; Delay Chain Summary ;
+----------+----------+---------------+---------------+-----------------------+-----+
; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ;
+----------+----------+---------------+---------------+-----------------------+-----+
; Tone[0] ; Input ; ON ; ON ; -- ; -- ;
; Tone[1] ; Input ; ON ; ON ; -- ; -- ;
; Tone[2] ; Input ; ON ; ON ; -- ; -- ;
; Tone[3] ; Input ; ON ; ON ; -- ; -- ;
; Tone[4] ; Input ; ON ; ON ; -- ; -- ;
; Tone[5] ; Input ; OFF ; ON ; -- ; -- ;
; Tone[6] ; Input ; ON ; ON ; -- ; -- ;
; Tone[7] ; Input ; ON ; ON ; -- ; -- ;
; Tone[9] ; Input ; ON ; ON ; -- ; -- ;
; Tone[10] ; Input ; ON ; ON ; -- ; -- ;
; Tone[8] ; Input ; OFF ; ON ; -- ; -- ;
; clk ; Input ; OFF ; OFF ; -- ; -- ;
; SpkS ; Output ; -- ; -- ; -- ; -- ;
+----------+----------+---------------+---------------+-----------------------+-----+
+--------------------------------------------------------------------------------------------------------------------+
; Pad To Core Delay Chain Fanout ;
+--------------------------------------------------------------------------------------+-------------------+---------+
; Source Pin / Fanout ; Pad To Core Index ; Setting ;
+--------------------------------------------------------------------------------------+-------------------+---------+
; Tone[0] ; ; ;
; - lpm_counter:\GenSpkS:Count11[0]_rtl_0|cntr_7t7:auto_generated|counter_cella0 ; 0 ; ON ;
; Tone[1] ; ; ;
; - lpm_counter:\GenSpkS:Count11[0]_rtl_0|cntr_7t7:auto_generated|counter_cella1 ; 0 ; ON ;
; Tone[2] ; ; ;
; - lpm_counter:\GenSpkS:Count11[0]_rtl_0|cntr_7t7:auto_generated|counter_cella2 ; 0 ; ON ;
; Tone[3] ; ; ;
; - lpm_counter:\GenSpkS:Count11[0]_rtl_0|cntr_7t7:auto_generated|counter_cella3 ; 0 ; ON ;
; Tone[4] ; ; ;
; - lpm_counter:\GenSpkS:Count11[0]_rtl_0|cntr_7t7:auto_generated|counter_cella4 ; 0 ; ON ;
; Tone[5] ; ; ;
; - lpm_counter:\GenSpkS:Count11[0]_rtl_0|cntr_7t7:auto_generated|counter_cella5 ; 1 ; ON ;
; Tone[6] ; ; ;
; - lpm_counter:\GenSpkS:Count11[0]_rtl_0|cntr_7t7:auto_generated|counter_cella6 ; 0 ; ON ;
; Tone[7] ; ; ;
; - lpm_counter:\GenSpkS:Count11[0]_rtl_0|cntr_7t7:auto_generated|counter_cella7 ; 0 ; ON ;
; Tone[9] ; ; ;
; - lpm_counter:\GenSpkS:Count11[0]_rtl_0|cntr_7t7:auto_generated|counter_cella9 ; 0 ; ON ;
; Tone[10] ; ; ;
; - lpm_counter:\GenSpkS:Count11[0]_rtl_0|cntr_7t7:auto_generated|counter_cella10 ; 0 ; ON ;
; Tone[8] ; ; ;
; - lpm_counter:\GenSpkS:Count11[0]_rtl_0|cntr_7t7:auto_generated|counter_cella8 ; 1 ; ON ;
; clk ; ; ;
+--------------------------------------------------------------------------------------+-------------------+---------+
+-----------------------------------------------------------------------------------------------------------------+
; Control Signals ;
+---------------+--------------+---------+---------------------+--------+----------------------+------------------+
; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
+---------------+--------------+---------+---------------------+--------+----------------------+------------------+
; FullSpkS ; LC_X26_Y8_N6 ; 1 ; Clock ; no ; -- ; -- ;
; PreCLK~15 ; LC_X12_Y7_N2 ; 16 ; Async. clear, Clock ; yes ; Global clock ; GCLK3 ;
; clk ; PIN_10 ; 4 ; Clock ; yes ; Global clock ; GCLK2 ;
; reduce_nor~71 ; LC_X26_Y8_N6 ; 11 ; Sync. load ; no ; -- ; -- ;
+---------------+--------------+---------+---------------------+--------+----------------------+------------------+
+------------------------------------------------------------------------------+
; Global & Other Fast Signals ;
+-----------+--------------+---------+----------------------+------------------+
; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ;
+-----------+--------------+---------+----------------------+------------------+
; PreCLK~15 ; LC_X12_Y7_N2 ; 16 ; Global clock ; GCLK3 ;
; clk ; PIN_10 ; 4 ; Global clock ; GCLK2 ;
+-----------+--------------+---------+----------------------+------------------+
+---------------------------------------------------------------------------------------------+
; Non-Global High Fan-Out Signals ;
+-----------------------------------------------------------------------------------+---------+
; Name ; Fan-Out ;
+-----------------------------------------------------------------------------------+---------+
; reduce_nor~71 ; 11 ;
; lpm_counter:\GenSpkS:Count11[0]_rtl_0|cntr_7t7:auto_generated|counter_cella4~COUT ; 5 ;
; lpm_counter:\DivideCLK:Count4[0]_rtl_1|cntr_ea7:auto_generated|safe_q[3] ; 2 ;
; lpm_counter:\DivideCLK:Count4[0]_rtl_1|cntr_ea7:auto_generated|safe_q[2] ; 2 ;
; lpm_counter:\GenSpkS:Count11[0]_rtl_0|cntr_7t7:auto_generated|safe_q[8] ; 2 ;
; lpm_counter:\GenSpkS:Count11[0]_rtl_0|cntr_7t7:auto_generated|safe_q[10] ; 2 ;
; lpm_counter:\GenSpkS:Count11[0]_rtl_0|cntr_7t7:auto_generated|safe_q[9] ; 2 ;
; lpm_counter:\GenSpkS:Count11[0]_rtl_0|cntr_7t7:auto_generated|safe_q[7] ; 2 ;
; lpm_counter:\GenSpkS:Count11[0]_rtl_0|cntr_7t7:auto_generated|safe_q[6] ; 2 ;
; lpm_counter:\GenSpkS:Count11[0]_rtl_0|cntr_7t7:auto_generated|safe_q[5] ; 2 ;
; lpm_counter:\GenSpkS:Count11[0]_rtl_0|cntr_7t7:auto_generated|safe_q[4] ; 2 ;
; lpm_counter:\GenSpkS:Count11[0]_rtl_0|cntr_7t7:auto_generated|safe_q[3] ; 2 ;
; lpm_counter:\GenSpkS:Count11[0]_rtl_0|cntr_7t7:auto_generated|safe_q[2] ; 2 ;
; lpm_counter:\GenSpkS:Count11[0]_rtl_0|cntr_7t7:auto_generated|safe_q[1] ; 2 ;
; lpm_counter:\GenSpkS:Count11[0]_rtl_0|cntr_7t7:auto_generated|safe_q[0] ; 2 ;
; \DelaySpkS:Count2 ; 2 ;
; Tone[8] ; 1 ;
; Tone[10] ; 1 ;
; Tone[9] ; 1 ;
; Tone[7] ; 1 ;
; Tone[6] ; 1 ;
; Tone[5] ; 1 ;
; Tone[4] ; 1 ;
; Tone[3] ; 1 ;
; Tone[2] ; 1 ;
; Tone[1] ; 1 ;
; Tone[0] ; 1 ;
; lpm_counter:\DivideCLK:Count4[0]_rtl_1|cntr_ea7:auto_generated|safe_q[0]~COUT1 ; 1 ;
; lpm_counter:\DivideCLK:Count4[0]_rtl_1|cntr_ea7:auto_generated|safe_q[0]~COUT0 ; 1 ;
; lpm_counter:\DivideCLK:Count4[0]_rtl_1|cntr_ea7:auto_generated|safe_q[0] ; 1 ;
; lpm_counter:\DivideCLK:Count4[0]_rtl_1|cntr_ea7:auto_generated|safe_q[1]~COUT1 ; 1 ;
; lpm_counter:\DivideCLK:Count4[0]_rtl_1|cntr_ea7:auto_generated|safe_q[1]~COUT0 ; 1 ;
; lpm_counter:\DivideCLK:Count4[0]_rtl_1|cntr_ea7:auto_generated|safe_q[1] ; 1 ;
; lpm_counter:\DivideCLK:Count4[0]_rtl_1|cntr_ea7:auto_generated|safe_q[2]~COUT1 ; 1 ;
; lpm_counter:\DivideCLK:Count4[0]_rtl_1|cntr_ea7:auto_generated|safe_q[2]~COUT0 ; 1 ;
; FullSpkS ; 1 ;
; lpm_counter:\GenSpkS:Count11[0]_rtl_0|cntr_7t7:auto_generated|safe_q[8]~COUT1 ; 1 ;
; lpm_counter:\GenSpkS:Count11[0]_rtl_0|cntr_7t7:auto_generated|safe_q[8]~COUT0 ; 1 ;
; reduce_nor~70 ; 1 ;
; lpm_counter:\GenSpkS:Count11[0]_rtl_0|cntr_7t7:auto_generated|counter_cella9~COUT ; 1 ;
; reduce_nor~69 ; 1 ;
; lpm_counter:\GenSpkS:Count11[0]_rtl_0|cntr_7t7:auto_generated|safe_q[7]~COUT1 ; 1 ;
; lpm_counter:\GenSpkS:Count11[0]_rtl_0|cntr_7t7:auto_generated|safe_q[7]~COUT0 ; 1 ;
; lpm_counter:\GenSpkS:Count11[0]_rtl_0|cntr_7t7:auto_generated|safe_q[6]~COUT1 ; 1 ;
; lpm_counter:\GenSpkS:Count11[0]_rtl_0|cntr_7t7:auto_generated|safe_q[6]~COUT0 ; 1 ;
; lpm_counter:\GenSpkS:Count11[0]_rtl_0|cntr_7t7:auto_generated|safe_q[5]~COUT1 ; 1 ;
; lpm_counter:\GenSpkS:Count11[0]_rtl_0|cntr_7t7:auto_generated|safe_q[5]~COUT0 ; 1 ;
; reduce_nor~68 ; 1 ;
; lpm_counter:\GenSpkS:Count11[0]_rtl_0|cntr_7t7:auto_generated|safe_q[3]~COUT1 ; 1 ;
; lpm_counter:\GenSpkS:Count11[0]_rtl_0|cntr_7t7:auto_generated|safe_q[3]~COUT0 ; 1 ;
+-----------------------------------------------------------------------------------+---------+
+----------------------------------------------------+
; Interconnect Usage Summary ;
+----------------------------+-----------------------+
; Interconnect Resource Type ; Usage ;
+----------------------------+-----------------------+
; C4s ; 18 / 8,840 ( < 1 % ) ;
; Direct links ; 3 / 11,506 ( < 1 % ) ;
; Global clocks ; 2 / 8 ( 25 % ) ;
; LAB clocks ; 4 / 156 ( 2 % ) ;
; LUT chains ; 0 / 2,619 ( 0 % ) ;
; Local interconnects ; 19 / 11,506 ( < 1 % ) ;
; M4K buffers ; 0 / 468 ( 0 % ) ;
; R4s ; 5 / 7,520 ( < 1 % ) ;
+----------------------------+-----------------------+
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