ddsa.map.rpt

基于ALTERA CYCLONE 系列的音乐播放示例实验教程.

; Number of synthesis-generated cells                    ; 7     ;
; Number of WYSIWYG LUTs                                 ; 15    ;
; Number of synthesis-generated LUTs                     ; 5     ;
; Number of WYSIWYG registers                            ; 15    ;
; Number of synthesis-generated registers                ; 2     ;
; Number of cells with combinational logic only          ; 5     ;
; Number of cells with registers only                    ; 2     ;
; Number of cells with combinational logic and registers ; 15    ;
+--------------------------------------------------------+-------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 11    ;
; Number of registers using Asynchronous Clear ; 4     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Output Enable      ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-----------+
; Hierarchy ;
+-----------+
ddsa
 |-- lpm_counter:\DivideCLK:Count4[0]_rtl_1
      |-- cntr_ea7:auto_generated
 |-- lpm_counter:\GenSpkS:Count11[0]_rtl_0
      |-- cntr_7t7:auto_generated


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                         ;
+---------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+----------------------------------------------------------------------+
; Compilation Hierarchy Node                  ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name                                                  ;
+---------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+----------------------------------------------------------------------+
; |ddsa                                       ; 22 (7)      ; 17           ; 0           ; 13   ; 0            ; 5 (5)        ; 2 (2)             ; 15 (0)           ; 15 (0)          ; |ddsa                                                                ;
;    |lpm_counter:\DivideCLK:Count4[0]_rtl_1| ; 4 (0)       ; 4            ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (0)            ; 4 (0)           ; |ddsa|lpm_counter:\DivideCLK:Count4[0]_rtl_1                         ;
;       |cntr_ea7:auto_generated|             ; 4 (4)       ; 4            ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (4)            ; 4 (4)           ; |ddsa|lpm_counter:\DivideCLK:Count4[0]_rtl_1|cntr_ea7:auto_generated ;
;    |lpm_counter:\GenSpkS:Count11[0]_rtl_0|  ; 11 (0)      ; 11           ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 11 (0)           ; 11 (0)          ; |ddsa|lpm_counter:\GenSpkS:Count11[0]_rtl_0                          ;
;       |cntr_7t7:auto_generated|             ; 11 (11)     ; 11           ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 11 (11)          ; 11 (11)         ; |ddsa|lpm_counter:\GenSpkS:Count11[0]_rtl_0|cntr_7t7:auto_generated  ;
+---------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+----------------------------------------------------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in h:/jspx/eda-1c6/music1/ddsa.map.eqn.


+--------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                         ;
+--------------------------------------------------------------+-----------------+
; File Name                                                    ; Used in Netlist ;
+--------------------------------------------------------------+-----------------+
; ddsa.vhd                                                     ; yes             ;
; g:/altera/quartus41/libraries/megafunctions/lpm_counter.tdf  ; yes             ;
; g:/altera/quartus41/libraries/megafunctions/lpm_constant.inc ; yes             ;
; h:/jspx/eda-1c6/music1/db/cntr_7t7.tdf                       ; yes             ;
; h:/jspx/eda-1c6/music1/db/cntr_ea7.tdf                       ; yes             ;
+--------------------------------------------------------------+-----------------+


+-----------------------------------------------+
; Analysis & Synthesis Resource Usage Summary   ;
+-----------------------------------+-----------+
; Resource                          ; Usage     ;
+-----------------------------------+-----------+
; Logic cells                       ; 22        ;
; Total combinational functions     ; 20        ;
; Total 4-input functions           ; 3         ;
; Total 3-input functions           ; 0         ;
; Total 2-input functions           ; 2         ;
; Total 1-input functions           ; 15        ;
; Total 0-input functions           ; 0         ;
; Combinational cells for routing   ; 0         ;
; Total registers                   ; 17        ;
; Total logic cells in carry chains ; 15        ;
; I/O pins                          ; 13        ;
; Maximum fan-out node              ; PreCLK~15 ;
; Maximum fan-out                   ; 16        ;
; Total fan-out                     ; 90        ;
; Average fan-out                   ; 2.57      ;
+-----------------------------------+-----------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
    Info: Processing started: Sun Dec 12 12:02:23 2004
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off ddsa -c ddsa
Info: Found 2 design units, including 1 entities, in source file ddsa.vhd
    Info: Found design unit 1: ddsa-one
    Info: Found entity 1: ddsa
Info: Duplicate registers merged to single register
    Info: Duplicate register SpkS~reg0 merged to single register \DelaySpkS:Count2
Info: Inferred 2 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=11) from the following logic: \GenSpkS:Count11[0]~0
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \DivideCLK:Count4[0]~0
Info: Found 1 design units, including 1 entities, in source file g:/altera/quartus41/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Found 1 design units, including 1 entities, in source file db/cntr_7t7.tdf
    Info: Found entity 1: cntr_7t7
Info: Found 1 design units, including 1 entities, in source file db/cntr_ea7.tdf
    Info: Found entity 1: cntr_ea7
Info: Implemented 35 device resources after synthesis - the final resource count might be different
    Info: Implemented 12 input pins
    Info: Implemented 1 output pins
    Info: Implemented 22 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Processing ended: Sun Dec 12 12:02:25 2004
    Info: Elapsed time: 00:00:01