tonetaba.rpt

基于ALTERA CYCLONE 系列的音乐播放示例实验教程.

_LC6_A2  = LCELL( _EQ029);
  _EQ029 = !_LC1_A8 &  _LC4_A2 & !_LC4_B3
         #  _LC6_A1;

-- Node name is ':979' 
-- Equation name is '_LC4_A2', type is buried 
_LC4_A2  = LCELL( _EQ030);
  _EQ030 = !_LC1_A11 &  _LC6_A2 &  _LC8_A2
         #  _LC1_A10;

-- Node name is ':1005' 
-- Equation name is '_LC5_B3', type is buried 
_LC5_B3  = LCELL( _EQ031);
  _EQ031 =  _LC1_B3 & !_LC3_B7 &  _LC7_B3
         #  _LC4_A9 &  _LC7_B3;

-- Node name is '~1017~1' 
-- Equation name is '~1017~1', location is LC1_B2, type is buried.
-- synthesized logic cell 
_LC1_B2  = LCELL( _EQ032);
  _EQ032 = !_LC2_A1 & !_LC6_A1;

-- Node name is ':1017' 
-- Equation name is '_LC6_B3', type is buried 
_LC6_B3  = LCELL( _EQ033);
  _EQ033 =  _LC1_B2 & !_LC3_A1 &  _LC5_B3
         #  _LC1_A12 &  _LC1_B2 & !_LC3_A1;

-- Node name is ':1021' 
-- Equation name is '_LC1_B3', type is buried 
_LC1_B3  = LCELL( _EQ034);
  _EQ034 = !_LC1_A11 &  _LC6_B3
         #  _LC1_A7 & !_LC1_A11
         #  _LC1_A10;

-- Node name is ':1047' 
-- Equation name is '_LC6_B4', type is buried 
_LC6_B4  = LCELL( _EQ035);
  _EQ035 =  _LC1_B4 & !_LC2_A4 & !_LC2_B4
         #  _LC1_A3 & !_LC2_A4;

-- Node name is ':1063' 
-- Equation name is '_LC1_B4', type is buried 
_LC1_B4  = LCELL( _EQ036);
  _EQ036 =  _LC1_C5 & !_LC3_B11
         #  _LC1_C5 &  _LC6_B4
         #  _LC1_A10;

-- Node name is ':1078' 
-- Equation name is '_LC1_B12', type is buried 
_LC1_B12 = LCELL( _EQ037);
  _EQ037 = !_LC2_A7 &  _LC6_B12
         #  _LC1_B10
         #  _LC1_A5;

-- Node name is ':1095' 
-- Equation name is '_LC2_B12', type is buried 
_LC2_B12 = LCELL( _EQ038);
  _EQ038 =  _LC1_B12 &  _LC2_B6 & !_LC3_A1
         #  _LC1_A12 & !_LC3_A1;

-- Node name is ':1105' 
-- Equation name is '_LC6_B12', type is buried 
_LC6_B12 = LCELL( _EQ039);
  _EQ039 = !_LC1_A7 &  _LC2_B12
         # !_LC1_A7 & !_LC1_B2
         #  _LC3_A2;

-- Node name is ':1128' 
-- Equation name is '_LC4_B8', type is buried 
_LC4_B8  = LCELL( _EQ040);
  _EQ040 = !_LC1_A3 &  _LC1_B10
         # !_LC1_A3 & !_LC3_B7 &  _LC3_B8;

-- Node name is ':1132' 
-- Equation name is '_LC6_B8', type is buried 
_LC6_B8  = LCELL( _EQ041);
  _EQ041 = !_LC1_A12 &  _LC4_B8
         # !_LC1_A12 &  _LC2_A4
         #  _LC3_A1;

-- Node name is ':1147' 
-- Equation name is '_LC3_B8', type is buried 
_LC3_B8  = LCELL( _EQ042);
  _EQ042 =  _LC1_B2 &  _LC1_C5 &  _LC6_B8
         #  _LC1_A10;

-- Node name is '~1179~1' 
-- Equation name is '~1179~1', location is LC7_B3, type is buried.
-- synthesized logic cell 
_LC7_B3  = LCELL( _EQ043);
  _EQ043 =  _LC2_B6 & !_LC3_A9;

-- Node name is ':1179' 
-- Equation name is '_LC7_A2', type is buried 
_LC7_A2  = LCELL( _EQ044);
  _EQ044 =  _LC1_A2 & !_LC1_A8 & !_LC4_B3;

-- Node name is '~1188~1' 
-- Equation name is '~1188~1', location is LC8_A2, type is buried.
-- synthesized logic cell 
_LC8_A2  = LCELL( _EQ045);
  _EQ045 = !_LC1_A7 & !_LC2_A1;

-- Node name is '~1189~1' 
-- Equation name is '~1189~1', location is LC3_A2, type is buried.
-- synthesized logic cell 
_LC3_A2  = LCELL( _EQ046);
  _EQ046 =  _LC1_A10
         #  _LC1_A11;

-- Node name is ':1189' 
-- Equation name is '_LC1_A2', type is buried 
_LC1_A2  = LCELL( _EQ047);
  _EQ047 =  _LC3_A2
         #  _LC6_A1 &  _LC8_A2
         #  _LC7_A2 &  _LC8_A2;

-- Node name is ':1201' 
-- Equation name is '_LC2_B3', type is buried 
_LC2_B3  = LCELL( _EQ048);
  _EQ048 = !_LC2_A7 &  _LC8_B3
         #  _LC1_A5
         #  _LC4_A9;

-- Node name is '~1215~1' 
-- Equation name is '~1215~1', location is LC2_B6, type is buried.
-- synthesized logic cell 
_LC2_B6  = LCELL( _EQ049);
  _EQ049 = !_LC1_A3 & !_LC2_A4;

-- Node name is '~1219~1' 
-- Equation name is '~1219~1', location is LC1_A8, type is buried.
-- synthesized logic cell 
!_LC1_A8 = _LC1_A8~NOT;
_LC1_A8~NOT = LCELL( _EQ050);
  _EQ050 = !_LC1_A12 & !_LC3_A1;

-- Node name is ':1219' 
-- Equation name is '_LC3_B3', type is buried 
_LC3_B3  = LCELL( _EQ051);
  _EQ051 =  _LC2_B3 &  _LC7_B3
         #  _LC6_A1
         #  _LC1_A8;

-- Node name is ':1231' 
-- Equation name is '_LC8_B3', type is buried 
_LC8_B3  = LCELL( _EQ052);
  _EQ052 = !_LC1_A7 & !_LC2_A1 & !_LC3_A2 &  _LC3_B3;

-- Node name is ':1240' 
-- Equation name is '_LC1_A9', type is buried 
_LC1_A9  = LCELL( _EQ053);
  _EQ053 = !_LC2_A7 &  _LC5_A2
         #  _LC1_A5;

-- Node name is ':1249' 
-- Equation name is '_LC5_A9', type is buried 
_LC5_A9  = LCELL( _EQ054);
  _EQ054 =  _LC1_A9 & !_LC4_A9
         #  _LC1_A3
         #  _LC3_A9;

-- Node name is ':1258' 
-- Equation name is '_LC2_A2', type is buried 
_LC2_A2  = LCELL( _EQ055);
  _EQ055 = !_LC2_A4 &  _LC5_A9
         #  _LC1_A8;

-- Node name is ':1273' 
-- Equation name is '_LC5_A2', type is buried 
_LC5_A2  = LCELL( _EQ056);
  _EQ056 =  _LC2_A2 & !_LC3_A2 & !_LC6_A1
         # !_LC3_A2 & !_LC8_A2;

-- Node name is '~1288~1' 
-- Equation name is '~1288~1', location is LC1_B10, type is buried.
-- synthesized logic cell 
_LC1_B10 = LCELL( _EQ057);
  _EQ057 =  _LC4_A9
         #  _LC3_A9;

-- Node name is ':1288' 
-- Equation name is '_LC2_A6', type is buried 
_LC2_A6  = LCELL( _EQ058);
  _EQ058 = !_LC1_A5 &  _LC6_A6
         # !_LC1_A5 &  _LC2_A7
         #  _LC1_B10;

-- Node name is ':1297' 
-- Equation name is '_LC3_A6', type is buried 
_LC3_A6  = LCELL( _EQ059);
  _EQ059 = !_LC1_A3 &  _LC2_A6
         #  _LC1_A12
         #  _LC2_A4;

-- Node name is ':1306' 
-- Equation name is '_LC1_A6', type is buried 
_LC1_A6  = LCELL( _EQ060);
  _EQ060 = !_LC3_A1 &  _LC3_A6
         #  _LC2_A1
         #  _LC6_A1;

-- Node name is ':1315' 
-- Equation name is '_LC6_A6', type is buried 
_LC6_A6  = LCELL( _EQ061);
  _EQ061 =  _LC1_A6 & !_LC1_A7 & !_LC1_A10
         # !_LC1_A10 &  _LC1_A11;

-- Node name is '~1336~1' 
-- Equation name is '~1336~1', location is LC4_B3, type is buried.
-- synthesized logic cell 
!_LC4_B3 = _LC4_B3~NOT;
_LC4_B3~NOT = LCELL( _EQ062);
  _EQ062 = !_LC3_B7 & !_LC4_A9 &  _LC7_B3;

-- Node name is ':1357' 
-- Equation name is '_LC5_C5', type is buried 
_LC5_C5  = LCELL( _EQ063);
  _EQ063 =  _LC3_C5 &  _LC5_C5
         #  _LC3_C5 &  _LC4_B3;

-- Node name is '~1359~1' 
-- Equation name is '~1359~1', location is LC1_C5, type is buried.
-- synthesized logic cell 
_LC1_C5  = LCELL( _EQ064);
  _EQ064 = !_LC1_A7 & !_LC1_A11;

-- Node name is '~1359~2' 
-- Equation name is '~1359~2', location is LC3_B11, type is buried.
-- synthesized logic cell 
!_LC3_B11 = _LC3_B11~NOT;
_LC3_B11~NOT = LCELL( _EQ065);
  _EQ065 =  _LC6_A1
         #  _LC1_A8
         #  _LC2_A1;

-- Node name is '~1359~3' 
-- Equation name is '~1359~3', location is LC3_C5, type is buried.
-- synthesized logic cell 
_LC3_C5  = LCELL( _EQ066);
  _EQ066 = !_LC1_A7 & !_LC1_A10 & !_LC1_A11 &  _LC3_B11;



Project Information                             e:\vhdldemo\music\tonetaba.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:01
   Partitioner                            00:00:00
   Fitter                                 00:00:02
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:04


Memory Allocated
-----------------

Peak memory allocated during compilation  = 10,865K