📄 songer.rpt
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Total logic cells required: 380
Total flipflops required: 26
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 189/1728 ( 10%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 EA 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Total(LC/EC)
A: 7 1 3 3 1 3 4 5 1 2 2 2 2 2 2 2 3 1 0 3 7 0 0 0 0 1 0 1 0 1 1 1 1 0 0 0 2 64/0
B: 1 8 0 1 0 1 1 1 3 2 0 0 0 0 1 0 6 8 0 0 0 0 7 0 0 8 0 0 7 0 0 0 0 0 6 2 0 63/0
C: 0 0 0 0 1 1 6 1 6 7 8 6 1 3 3 1 1 1 0 0 0 0 0 4 0 0 1 3 1 1 0 8 1 1 1 1 0 68/0
D: 3 8 1 0 5 8 8 0 1 0 1 0 1 1 1 5 1 0 0 0 0 0 8 0 0 0 0 8 1 0 0 0 0 0 1 6 0 68/0
E: 1 1 1 1 0 1 0 0 0 6 1 1 3 1 4 8 0 1 0 0 0 0 0 0 4 0 7 7 0 1 1 1 1 1 1 0 5 59/0
F: 0 0 0 1 7 0 1 7 1 0 0 0 0 0 0 0 4 0 0 0 0 8 1 8 7 1 3 1 1 0 1 0 0 0 0 1 5 58/0
Total: 12 18 5 6 14 14 20 14 12 17 12 9 7 7 11 16 15 11 0 3 7 8 16 12 11 10 11 20 10 3 3 10 3 2 9 10 12 380/0
Device-Specific Information: f:\xd_dsp\disk5\pk-1k30\music1\songer.rpt
songer
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
54 - - - -- INPUT ^ 0 0 0 8 CLK8HZ
124 - - - -- INPUT ^ 0 0 0 4 CLK12MHZ
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\xd_dsp\disk5\pk-1k30\music1\songer.rpt
songer
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
30 - - F -- OUTPUT 0 1 0 0 CODE10
31 - - F -- OUTPUT 0 1 0 0 CODE11
32 - - F -- OUTPUT 0 1 0 0 CODE12
33 - - F -- OUTPUT 0 1 0 0 CODE13
81 - - F -- OUTPUT 0 1 0 0 HIGH1
99 - - B -- OUTPUT 0 1 0 0 SPKOUT
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\xd_dsp\disk5\pk-1k30\music1\songer.rpt
songer
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 3 - A 05 AND2 0 3 0 8 |NoteTabs:u1|LPM_ADD_SUB:106|addcore:adder|:79
- 4 - A 08 AND2 0 4 0 4 |NoteTabs:u1|LPM_ADD_SUB:106|addcore:adder|:91
- 2 - A 08 OR2 ! 0 2 0 1 |NoteTabs:u1|LPM_ADD_SUB:106|addcore:adder|:95
- 6 - A 08 DFFE 1 3 0 20 |NoteTabs:u1|Counter7 (|NoteTabs:u1|:7)
- 1 - A 08 DFFE 1 2 0 16 |NoteTabs:u1|Counter6 (|NoteTabs:u1|:8)
- 2 - A 16 DFFE 1 4 0 14 |NoteTabs:u1|Counter5 (|NoteTabs:u1|:9)
- 1 - A 10 DFFE 1 3 0 11 |NoteTabs:u1|Counter4 (|NoteTabs:u1|:10)
- 4 - A 17 DFFE 1 4 0 12 |NoteTabs:u1|Counter3 (|NoteTabs:u1|:11)
- 1 - A 17 DFFE 1 3 0 13 |NoteTabs:u1|Counter2 (|NoteTabs:u1|:12)
- 2 - A 17 DFFE 1 2 0 14 |NoteTabs:u1|Counter1 (|NoteTabs:u1|:13)
- 5 - A 13 DFFE 1 1 0 14 |NoteTabs:u1|Counter0 (|NoteTabs:u1|:14)
- 1 - A 02 OR2 ! 0 4 0 8 |NoteTabs:u1|:48
- 7 - A 01 AND2 s 0 3 0 1 |NoteTabs:u1|~3308~1
- 3 - A 08 AND2 s 0 2 0 3 |NoteTabs:u1|~3328~1
- 8 - D 02 AND2 s ! 0 2 0 4 |NoteTabs:u1|~3388~1
- 5 - A 14 OR2 s 0 3 0 11 |NoteTabs:u1|~3488~1
- 1 - D 11 AND2 0 3 0 4 |NoteTabs:u1|:3528
- 2 - D 01 OR2 s ! 0 2 0 8 |NoteTabs:u1|~3708~1
- 7 - D 01 OR2 ! 0 2 0 1 |NoteTabs:u1|:3768
- 8 - D 06 AND2 0 2 0 3 |NoteTabs:u1|:3848
- 1 - D 09 AND2 s ! 0 2 0 3 |NoteTabs:u1|~3868~1
- 1 - A 15 OR2 s 0 4 0 4 |NoteTabs:u1|~3888~1
- 2 - A 31 OR2 s ! 0 3 0 16 |NoteTabs:u1|~4028~1
- 2 - C 32 AND2 s 0 2 0 8 |NoteTabs:u1|~4028~2
- 4 - C 23 AND2 s 0 2 0 1 |NoteTabs:u1|~4028~3
- 5 - D 28 OR2 s ! 0 2 0 6 |NoteTabs:u1|~4028~4
- 2 - A 07 OR2 s ! 0 3 0 1 |NoteTabs:u1|~4028~5
- 2 - A 19 OR2 s ! 0 3 0 9 |NoteTabs:u1|~4048~1
- 1 - B 28 OR2 s ! 0 2 0 5 |NoteTabs:u1|~4048~2
- 1 - A 19 OR2 s 0 3 0 25 |NoteTabs:u1|~4108~1
- 5 - C 33 AND2 s 0 2 0 5 |NoteTabs:u1|~4108~2
- 2 - C 28 OR2 s ! 0 4 0 2 |NoteTabs:u1|~4108~3
- 2 - A 03 OR2 s ! 0 3 0 9 |NoteTabs:u1|~4128~1
- 8 - D 27 AND2 s 0 2 0 3 |NoteTabs:u1|~4188~1
- 1 - A 09 AND2 s ! 0 3 0 6 |NoteTabs:u1|~4288~1
- 5 - D 35 OR2 s ! 0 2 0 4 |NoteTabs:u1|~4348~1
- 1 - A 20 AND2 s 0 2 0 7 |NoteTabs:u1|~4508~1
- 7 - A 20 OR2 ! 0 2 0 1 |NoteTabs:u1|:4588
- 2 - A 20 OR2 s 0 2 0 4 |NoteTabs:u1|~4668~1
- 6 - A 06 OR2 s 0 4 0 4 |NoteTabs:u1|~4688~1
- 1 - A 03 OR2 s ! 0 3 0 11 |NoteTabs:u1|~4768~1
- 2 - B 15 AND2 0 2 0 4 |NoteTabs:u1|:4928
- 5 - B 18 AND2 s ! 0 2 0 5 |NoteTabs:u1|~4988~1
- 4 - A 19 OR2 s 0 3 0 10 |NoteTabs:u1|~5108~1
- 3 - C 23 AND2 s 0 2 0 1 |NoteTabs:u1|~5108~2
- 2 - A 32 OR2 s 0 3 0 4 |NoteTabs:u1|~5128~1
- 1 - C 26 AND2 s 0 2 0 10 |NoteTabs:u1|~5128~2
- 4 - B 02 OR2 s 0 2 0 5 |NoteTabs:u1|~5148~1
- 7 - A 29 AND2 s 0 3 0 6 |NoteTabs:u1|~5188~1
- 2 - A 27 AND2 s 0 3 0 7 |NoteTabs:u1|~5208~1
- 2 - B 02 AND2 0 2 0 2 |NoteTabs:u1|:5228
- 1 - A 06 AND2 s ! 0 2 0 6 |NoteTabs:u1|~5248~1
- 6 - A 11 AND2 s ! 0 2 0 12 |NoteTabs:u1|~5328~1
- 3 - A 04 OR2 s ! 0 3 0 6 |NoteTabs:u1|~5408~1
- 2 - A 36 AND2 0 3 0 1 |NoteTabs:u1|:5428
- 1 - A 13 OR2 s 0 2 0 21 |NoteTabs:u1|~5488~1
- 1 - F 09 OR2 ! 0 2 0 3 |NoteTabs:u1|:5488
- 4 - A 01 AND2 0 3 0 1 |NoteTabs:u1|:5548
- 1 - A 18 AND2 s ! 0 2 0 14 |NoteTabs:u1|~5648~1
- 2 - F 05 AND2 s ! 0 2 0 3 |NoteTabs:u1|~5668~1
- 2 - A 04 OR2 s ! 0 3 0 8 |NoteTabs:u1|~5728~1
- 4 - A 20 AND2 0 3 0 1 |NoteTabs:u1|:5728
- 3 - A 16 OR2 s 0 2 0 16 |NoteTabs:u1|~5808~1
- 2 - A 06 OR2 s 0 4 0 4 |NoteTabs:u1|~5808~2
- 5 - A 03 OR2 s 0 3 0 12 |NoteTabs:u1|~5828~1
- 1 - A 12 AND2 0 4 0 1 |NoteTabs:u1|:5868
- 2 - C 35 AND2 s ! 0 2 0 7 |NoteTabs:u1|~6108~1
- 3 - C 27 OR2 ! 0 2 0 1 |NoteTabs:u1|:6128
- 7 - A 14 OR2 s ! 0 3 0 11 |NoteTabs:u1|~6208~1
- 2 - C 27 OR2 s 0 2 0 4 |NoteTabs:u1|~6428~1
- 2 - A 15 OR2 s ! 0 4 0 5 |NoteTabs:u1|~6448~1
- 1 - A 04 OR2 s 0 4 0 2 |NoteTabs:u1|~6528~1
- 3 - A 12 AND2 s ! 0 3 0 11 |NoteTabs:u1|~6688~1
- 5 - A 07 OR2 s ! 0 2 0 3 |NoteTabs:u1|~6748~1
- 2 - C 17 AND2 s ! 0 2 0 5 |NoteTabs:u1|~6908~1
- 1 - C 08 AND2 0 2 0 5 |NoteTabs:u1|:6948
- 7 - D 07 OR2 ! 0 4 0 1 |NoteTabs:u1|:7228
- 4 - D 27 OR2 s ! 0 4 0 2 |NoteTabs:u1|~7316~1
- 6 - D 07 OR2 s ! 0 4 0 2 |NoteTabs:u1|~7316~2
- 2 - D 06 OR2 s 0 4 0 2 |NoteTabs:u1|~7316~3
- 5 - D 07 AND2 s ! 0 4 0 1 |NoteTabs:u1|~7316~4
- 4 - D 07 OR2 ! 0 4 0 1 |NoteTabs:u1|:7327
- 7 - D 22 OR2 s 0 3 0 2 |NoteTabs:u1|~7364~1
- 4 - D 22 OR2 s ! 0 4 0 1 |NoteTabs:u1|~7364~2
- 5 - D 22 AND2 ! 0 4 0 1 |NoteTabs:u1|:7364
- 1 - B 17 OR2 ! 0 4 0 1 |NoteTabs:u1|:7405
- 2 - B 17 AND2 s 0 3 0 1 |NoteTabs:u1|~7424~1
- 4 - B 17 OR2 ! 0 4 0 1 |NoteTabs:u1|:7435
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