ddsa.tan.rpt

基于ALTERA CYCLONE 系列的音乐播放示例实验教程.

+---------------+-------------+-----------+----------+--------------------------------------------------------------------------+----------+
; N/A           ; None        ; 1.802 ns  ; Tone[7]  ; lpm_counter:\GenSpkS:Count11[0]_rtl_0|cntr_7t7:auto_generated|safe_q[7]  ; clk      ;
; N/A           ; None        ; 1.802 ns  ; Tone[3]  ; lpm_counter:\GenSpkS:Count11[0]_rtl_0|cntr_7t7:auto_generated|safe_q[3]  ; clk      ;
; N/A           ; None        ; 1.503 ns  ; Tone[1]  ; lpm_counter:\GenSpkS:Count11[0]_rtl_0|cntr_7t7:auto_generated|safe_q[1]  ; clk      ;
; N/A           ; None        ; 1.403 ns  ; Tone[10] ; lpm_counter:\GenSpkS:Count11[0]_rtl_0|cntr_7t7:auto_generated|safe_q[10] ; clk      ;
; N/A           ; None        ; 1.393 ns  ; Tone[2]  ; lpm_counter:\GenSpkS:Count11[0]_rtl_0|cntr_7t7:auto_generated|safe_q[2]  ; clk      ;
; N/A           ; None        ; 1.393 ns  ; Tone[0]  ; lpm_counter:\GenSpkS:Count11[0]_rtl_0|cntr_7t7:auto_generated|safe_q[0]  ; clk      ;
; N/A           ; None        ; 1.154 ns  ; Tone[5]  ; lpm_counter:\GenSpkS:Count11[0]_rtl_0|cntr_7t7:auto_generated|safe_q[5]  ; clk      ;
; N/A           ; None        ; 1.107 ns  ; Tone[9]  ; lpm_counter:\GenSpkS:Count11[0]_rtl_0|cntr_7t7:auto_generated|safe_q[9]  ; clk      ;
; N/A           ; None        ; 1.038 ns  ; Tone[6]  ; lpm_counter:\GenSpkS:Count11[0]_rtl_0|cntr_7t7:auto_generated|safe_q[6]  ; clk      ;
; N/A           ; None        ; 0.823 ns  ; Tone[8]  ; lpm_counter:\GenSpkS:Count11[0]_rtl_0|cntr_7t7:auto_generated|safe_q[8]  ; clk      ;
; N/A           ; None        ; 0.768 ns  ; Tone[4]  ; lpm_counter:\GenSpkS:Count11[0]_rtl_0|cntr_7t7:auto_generated|safe_q[4]  ; clk      ;
+---------------+-------------+-----------+----------+--------------------------------------------------------------------------+----------+


+-------------------------------------------------------------------------------------------+
; Minimum tco                                                                               ;
+---------------+------------------+----------------+-------------------+------+------------+
; Minimum Slack ; Required Min tco ; Actual Min tco ; From              ; To   ; From Clock ;
+---------------+------------------+----------------+-------------------+------+------------+
; N/A           ; None             ; 11.028 ns      ; \DelaySpkS:Count2 ; SpkS ; clk        ;
+---------------+------------------+----------------+-------------------+------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
    Info: Processing started: Sun Dec 12 12:02:32 2004
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off ddsa -c ddsa --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node clk is an undefined clock
Warning: Found 4 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock lpm_counter:\DivideCLK:Count4[0]_rtl_1|cntr_ea7:auto_generated|safe_q[2] as buffer
    Info: Detected ripple clock lpm_counter:\DivideCLK:Count4[0]_rtl_1|cntr_ea7:auto_generated|safe_q[3] as buffer
    Info: Detected gated clock PreCLK~15 as buffer
    Info: Detected ripple clock FullSpkS as buffer
Info: Clock clk has Internal fmax of 249.63 MHz between source register lpm_counter:\GenSpkS:Count11[0]_rtl_0|cntr_7t7:auto_generated|safe_q[1] and destination register lpm_counter:\GenSpkS:Count11[0]_rtl_0|cntr_7t7:auto_generated|safe_q[4] (period= 4.006 ns)
    Info: + Longest register to register delay is 3.768 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X26_Y9_N6; Fanout = 4; REG Node = 'lpm_counter:\GenSpkS:Count11[0]_rtl_0|cntr_7t7:auto_generated|safe_q[1]'
        Info: 2: + IC(0.413 ns) + CELL(0.454 ns) = 0.867 ns; Loc. = LC_X26_Y9_N4; Fanout = 2; COMB Node = 'reduce_nor~68'
        Info: 3: + IC(0.923 ns) + CELL(0.088 ns) = 1.878 ns; Loc. = LC_X26_Y8_N6; Fanout = 11; COMB Node = 'reduce_nor~71'
        Info: 4: + IC(0.947 ns) + CELL(0.943 ns) = 3.768 ns; Loc. = LC_X26_Y9_N9; Fanout = 3; REG Node = 'lpm_counter:\GenSpkS:Count11[0]_rtl_0|cntr_7t7:auto_generated|safe_q[4]'
        Info: Total cell delay = 1.485 ns ( 39.41 % )
        Info: Total interconnect delay = 2.283 ns ( 60.59 % )
    Info: - Smallest clock skew is -0.036 ns
        Info: + Shortest clock path from clock clk to destination register is 6.487 ns
            Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 4; CLK Node = 'clk'
            Info: 2: + IC(0.412 ns) + CELL(0.720 ns) = 2.262 ns; Loc. = LC_X12_Y7_N9; Fanout = 2; REG Node = 'lpm_counter:\DivideCLK:Count4[0]_rtl_1|cntr_ea7:auto_generated|safe_q[3]'
            Info: 3: + IC(0.427 ns) + CELL(0.225 ns) = 2.914 ns; Loc. = LC_X12_Y7_N2; Fanout = 16; COMB Node = 'PreCLK~15'
            Info: 4: + IC(3.026 ns) + CELL(0.547 ns) = 6.487 ns; Loc. = LC_X26_Y9_N9; Fanout = 3; REG Node = 'lpm_counter:\GenSpkS:Count11[0]_rtl_0|cntr_7t7:auto_generated|safe_q[4]'
            Info: Total cell delay = 2.622 ns ( 40.42 % )
            Info: Total interconnect delay = 3.865 ns ( 59.58 % )
        Info: - Longest clock path from clock clk to source register is 6.523 ns
            Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 4; CLK Node = 'clk'
            Info: 2: + IC(0.412 ns) + CELL(0.720 ns) = 2.262 ns; Loc. = LC_X12_Y7_N8; Fanout = 4; REG Node = 'lpm_counter:\DivideCLK:Count4[0]_rtl_1|cntr_ea7:auto_generated|safe_q[2]'
            Info: 3: + IC(0.600 ns) + CELL(0.088 ns) = 2.950 ns; Loc. = LC_X12_Y7_N2; Fanout = 16; COMB Node = 'PreCLK~15'
            Info: 4: + IC(3.026 ns) + CELL(0.547 ns) = 6.523 ns; Loc. = LC_X26_Y9_N6; Fanout = 4; REG Node = 'lpm_counter:\GenSpkS:Count11[0]_rtl_0|cntr_7t7:auto_generated|safe_q[1]'
            Info: Total cell delay = 2.485 ns ( 38.10 % )
            Info: Total interconnect delay = 4.038 ns ( 61.90 % )
    Info: + Micro clock to output delay of source is 0.173 ns
    Info: + Micro setup delay of destination is 0.029 ns
Info: tsu for register lpm_counter:\GenSpkS:Count11[0]_rtl_0|cntr_7