📄 songer.map.rpt
字号:
+----------------------------------------------+-------+
+-----------+
; Hierarchy ;
+-----------+
Songer
|-- NoteTabs:u1
|-- lpm_counter:Counter_rtl_0
|-- cntr_ia7:auto_generated
|-- ToneTaba:u2
|-- Speakera:u3
|-- lpm_counter:\DivideCLK:Count4[0]_rtl_2
|-- cntr_ea7:auto_generated
|-- lpm_counter:\GenSpkS:Count11[0]_rtl_1
|-- cntr_7t7:auto_generated
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+------------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------------------------------------------------------------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+------------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------------------------------------------------------------------------------+
; |Songer ; 121 (0) ; 25 ; 0 ; 8 ; 0 ; 96 (0) ; 2 (0) ; 23 (0) ; 23 (0) ; |Songer ;
; |NoteTabs:u1| ; 85 (77) ; 8 ; 0 ; 0 ; 0 ; 77 (77) ; 0 (0) ; 8 (0) ; 8 (0) ; |Songer|NoteTabs:u1 ;
; |lpm_counter:Counter_rtl_0| ; 8 (0) ; 8 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 8 (0) ; 8 (0) ; |Songer|NoteTabs:u1|lpm_counter:Counter_rtl_0 ;
; |cntr_ia7:auto_generated| ; 8 (8) ; 8 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 8 (8) ; 8 (8) ; |Songer|NoteTabs:u1|lpm_counter:Counter_rtl_0|cntr_ia7:auto_generated ;
; |Speakera:u3| ; 22 (7) ; 17 ; 0 ; 0 ; 0 ; 5 (5) ; 2 (2) ; 15 (0) ; 15 (0) ; |Songer|Speakera:u3 ;
; |lpm_counter:\DivideCLK:Count4[0]_rtl_2| ; 4 (0) ; 4 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 4 (0) ; 4 (0) ; |Songer|Speakera:u3|lpm_counter:\DivideCLK:Count4[0]_rtl_2 ;
; |cntr_ea7:auto_generated| ; 4 (4) ; 4 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 4 (4) ; 4 (4) ; |Songer|Speakera:u3|lpm_counter:\DivideCLK:Count4[0]_rtl_2|cntr_ea7:auto_generated ;
; |lpm_counter:\GenSpkS:Count11[0]_rtl_1| ; 11 (0) ; 11 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 11 (0) ; 11 (0) ; |Songer|Speakera:u3|lpm_counter:\GenSpkS:Count11[0]_rtl_1 ;
; |cntr_7t7:auto_generated| ; 11 (11) ; 11 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 11 (11) ; 11 (11) ; |Songer|Speakera:u3|lpm_counter:\GenSpkS:Count11[0]_rtl_1|cntr_7t7:auto_generated ;
; |ToneTaba:u2| ; 14 (14) ; 0 ; 0 ; 0 ; 0 ; 14 (14) ; 0 (0) ; 0 (0) ; 0 (0) ; |Songer|ToneTaba:u2 ;
+------------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------------------------------------------------------------------------------+
+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in F:/eda/EDA-1C6/EDA-1C6/Music1/SONGER.map.eqn.
+--------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+--------------------------------------------------------------+-----------------+
; File Name ; Used in Netlist ;
+--------------------------------------------------------------+-----------------+
; notetabs.vhd ; yes ;
; tonetaba.vhd ; yes ;
; speakera.vhd ; yes ;
; songer.vhd ; yes ;
; d:/altera/quartus41/libraries/megafunctions/lpm_counter.tdf ; yes ;
; d:/altera/quartus41/libraries/megafunctions/lpm_constant.inc ; yes ;
; F:/eda/EDA-1C6/EDA-1C6/Music1/db/cntr_ia7.tdf ; yes ;
; F:/eda/EDA-1C6/EDA-1C6/Music1/db/cntr_7t7.tdf ; yes ;
; F:/eda/EDA-1C6/EDA-1C6/Music1/db/cntr_ea7.tdf ; yes ;
+--------------------------------------------------------------+-----------------+
+-------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+-----------------------------------+-------------------------------------------------------------------------+
; Resource ; Usage ;
+-----------------------------------+-------------------------------------------------------------------------+
; Logic cells ; 121 ;
; Total combinational functions ; 119 ;
; Total 4-input functions ; 86 ;
; Total 3-input functions ; 5 ;
; Total 2-input functions ; 5 ;
; Total 1-input functions ; 23 ;
; Total 0-input functions ; 0 ;
; Combinational cells for routing ; 0 ;
; Total registers ; 25 ;
; Total logic cells in carry chains ; 23 ;
; I/O pins ; 8 ;
; Maximum fan-out node ; NoteTabs:u1|lpm_counter:Counter_rtl_0|cntr_ia7:auto_generated|safe_q[0] ;
; Maximum fan-out ; 43 ;
; Total fan-out ; 478 ;
; Average fan-out ; 3.71 ;
+-----------------------------------+-------------------------------------------------------------------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
Info: Processing started: Tue Jul 12 14:42:38 2005
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off SONGER -c SONGER
Info: Found 2 design units, including 1 entities, in source file notetabs.vhd
Info: Found design unit 1: NoteTabs-one
Info: Found entity 1: NoteTabs
Info: Found 2 design units, including 1 entities, in source file tonetaba.vhd
Info: Found design unit 1: ToneTaba-one
Info: Found entity 1: ToneTaba
Info: Found 2 design units, including 1 entities, in source file speakera.vhd
Info: Found design unit 1: Speakera-one
Info: Found entity 1: Speakera
Info: Found 2 design units, including 1 entities, in source file songer.vhd
Info: Found design unit 1: Songer-one
Info: Found entity 1: Songer
Warning: VHDL Process Statement warning at notetabs.vhd(12): signal counter is in statement, but is not in sensitivity list
Info: VHDL Case Statement information at notetabs.vhd(233): OTHERS choice is never selected
Warning: VHDL Process Statement warning at tonetaba.vhd(11): signal or variable tone may not be assigned a new value in every possible path through the Process Statement. Signal or variable tone holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: VHDL Process Statement warning at tonetaba.vhd(11): signal or variable code may not be assigned a new value in every possible path through the Process Statement. Signal or variable code holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: VHDL Process Statement warning at tonetaba.vhd(11): signal or variable high may not be assigned a new value in every possible path through the Process Statement. Signal or variable high holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Info: Ignored 16 buffer(s)
Info: Ignored 16 SOFT buffer(s)
Info: Duplicate registers merged to single register
Info: Duplicate register Speakera:u3|SpkS merged to single register Speakera:u3|\DelaySpkS:Count2
Warning: LATCH primitive ToneTaba:u2|CODE[3] is permanently enabled
Warning: LATCH primitive ToneTaba:u2|CODE[2] is permanently enabled
Warning: LATCH primitive ToneTaba:u2|CODE[1] is permanently enabled
Warning: LATCH primitive ToneTaba:u2|CODE[0] is permanently enabled
Warning: LATCH primitive ToneTaba:u2|HIGH is permanently enabled
Warning: LATCH primitive ToneTaba:u2|Tone[10] is permanently enabled
Warning: LATCH primitive ToneTaba:u2|Tone[9] is permanently enabled
Warning: LATCH primitive ToneTaba:u2|Tone[8] is permanently enabled
Warning: LATCH primitive ToneTaba:u2|Tone[7] is permanently enabled
Warning: LATCH primitive ToneTaba:u2|Tone[6] is permanently enabled
Warning: LATCH primitive ToneTaba:u2|Tone[5] is permanently enabled
Warning: LATCH primitive ToneTaba:u2|Tone[4] is permanently enabled
Warning: LATCH primitive ToneTaba:u2|Tone[3] is permanently enabled
Warning: LATCH primitive ToneTaba:u2|Tone[2] is permanently enabled
Warning: LATCH primitive ToneTaba:u2|Tone[1] is permanently enabled
Warning: LATCH primitive ToneTaba:u2|Tone[0] is permanently enabled
Info: Inferred 3 megafunctions from design logic
Info: Inferred lpm_counter megafunction (LPM_WIDTH=8) from the following logic: NoteTabs:u1|Counter[0]~0
Info: Inferred lpm_counter megafunction (LPM_WIDTH=11) from the following logic: Speakera:u3|\GenSpkS:Count11[0]~0
Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: Speakera:u3|\DivideCLK:Count4[0]~0
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus41/libraries/megafunctions/lpm_counter.tdf
Info: Found entity 1: lpm_counter
Info: Found 1 design units, including 1 entities, in source file db/cntr_ia7.tdf
Info: Found entity 1: cntr_ia7
Info: Found 1 design units, including 1 entities, in source file db/cntr_7t7.tdf
Info: Found entity 1: cntr_7t7
Info: Found 1 design units, including 1 entities, in source file db/cntr_ea7.tdf
Info: Found entity 1: cntr_ea7
Warning: Output pins are stuck at VCC or GND
Warning: Pin CODE1[3] stuck at GND
Info: Implemented 129 device resources after synthesis - the final resource count might be different
Info: Implemented 2 input pins
Info: Implemented 6 output pins
Info: Implemented 121 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 22 warnings
Info: Processing ended: Tue Jul 12 14:42:48 2005
Info: Elapsed time: 00:00:09
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -