speakera.vhd

来自「基于ALTERA CYCLONE 系列的音乐播放示例实验教程.」· VHDL 代码 · 共 52 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY Speakera IS
    PORT (  clk  : IN STD_LOGIC;
             Tone : IN INTEGER RANGE 0 TO 16#7FF#;
             SpkS : OUT STD_LOGIC  );
END;
ARCHITECTURE one OF Speakera IS
    SIGNAL PreCLK : STD_LOGIC;
    SIGNAL FullSpkS : STD_LOGIC;
BEGIN
 DivideCLK : PROCESS(clk)
        VARIABLE Count4 : INTEGER RANGE 0 TO 15;
    BEGIN
        PreCLK <= '0';
                --  将CLK进行16分频，PreCLK为CLK的16分频
        IF Count4 > 11  THEN  
            PreCLK <= '1';
            Count4 := 0;
        ELSIF clk'EVENT AND clk = '1' THEN
            Count4 := Count4 + 1;            
        END IF;
    END PROCESS;
    GenSpkS : PROCESS(PreCLK, Tone)
        VARIABLE Count11 : INTEGER RANGE 0 TO 16#7FF#;
BEGIN
            -- 11位可预置计数器
        IF PreCLK'EVENT AND PreCLK = '1' THEN
            IF Count11 = 16#7FF# THEN
                Count11 := Tone;
                FullSpkS <= '1';                
            ELSE
                Count11 := Count11 + 1;
                FullSpkS <= '0';                
            END IF;
        END IF;
    END PROCESS;
    DelaySpkS : PROCESS(FullSpkS)
        VARIABLE Count2 : STD_LOGIC;
BEGIN
                 -- 将输出再进行2分频，将脉冲展宽，以使扬声器有足够功率发音
        IF FullSpkS'EVENT AND FullSpkS = '1' THEN
            Count2 := NOT Count2;
            IF Count2 = '1' THEN  SpkS <= '1';
            ELSE
                SpkS <= '0';
            END IF;
        END IF;
    END PROCESS;
END;