cdrom1.txt

AVR单片机控制实现播放CD音频数据

//NEW DEFINE
#include <mega16.h>
#include <delay.h>
#define   Bit          bit
#define   Uchar        unsigned char
#define   Uint         unsigned int
#define   Ulong        unsigned long
//CD ROM CONTRL
#define   ATA_ADDR    PORTD
#define   ATA_DIOR	PORTD
#define   ATA_DIOW	PORTD
#define   ATA_RESET	PORTD
#define   ATA_INTRQ	PORTD
#define   ATA_INTRQ_DDR
#define   ATA_CS1   0X10
#define   ATA_CS3   0X10
//16B data bus
#define   ATA_DATA_LS  PORTD       //low  bus
#define   ATA_DATA_MS  PORTD       //high bus
#define   ATA_DATA_MS_OUT  DDRA=0XFF;
#define   ATA_DATA_LS_OUT  DDRB=0XFF;
#define   ATA_DATA_MS_IN   DDRA=0;
#define   ATA_DATA_LS_IN   DDRB=0;
//CD ROM REGISTER                //DA2 DA1 DA0
#define   DATA_REG                 000
#define   ERROR_REG                001
#define   SECTOR_C_REG             010
#define   SECTOR_N_REG             011
#define   CYLINDER_LOW_REG         100
#define   CYLINDER_HIGH_REG        101
#define   DEHEAD_REG               110
#define   COMMADN_REG              111
//ERROR RGE
#define   ERROR_REG_AMNF               0X01
#define   ERROR_REG_TKONF              0X02
#define   ERROR_REG_ABRT               0X04
#define   ERROR_REG_MCR                0X08
#define   ERROR_REG_IDNF               0X10
#define   ERROR_REG_MC                 0X20
#define   ERROR_REG_UNC                0X40
#define   ERROR_REG_RES                0X80
//STATUS REGISTER
#define   STATUS_REG_ERR               0X01
#define   STATUS_REG_IDX               0X02
#define   STATUS_REG_CORR              0X04
#define   STATUS_REG_DRQ               0X08
#define   STATUS_REG_DSC               0X10
#define   STATUS_REG_DF                0X20
#define   STATUS_REG_DRDY              0X40
#define   STATUS_REG_BSY               0X80
//ATAPI COMMAND set
#define   PLAY                         0X47
#define   STOP                         0X1B
#define   PAUSE                        0X4B
#define   EJECT                        0X1B
#define   CLOSE                        0X1B
#define   READ_TOC                     0X43
//ATA command set
#define   EXECUTE_DRIVE_DIAGNOSTICS    0X90
#define   ATAPI_PACKET                 0XA0
//FUNCTION
///////////////////////////////////////
/*           communication           */
///////////////////////////////////////
Uint read_cycle(void){
          Uint Temp;
          ATA_DATA_MS_IN;
          ATA_DATA_LS_IN;
          ATA_DIOR=0;
          Temp=(Uint)(ATA_DATA_LS+(Uint)(ATA_DATA_MS<<8));
          ATA_DIOR=1;
          return(Temp);
          }

Uchar read_cycle_l(void){
          Uchar Temp;
          ATA_DATA_LS_IN;
          ATA_DIOR=0;
          Temp=ATA_DATA_LS;
          ATA_DIOR=1;
          return(Temp);
          }

void write_cycle(Uint Data){
          ATA_DATA_MS_OUT;
          ATA_DATA_LS_OUT;
          ATA_DATA_MS=(Uchar)(Data>>8);
          ATA_DATA_LS=(Uchar)(Data);
          ATA_DIOW=0;
          delay_us(1);
          ATA_DIOW=1;
          }

void write_cycle_l(Uchar Data){
          ATA_DATA_LS_OUT;
          ATA_DATA_LS=Data;
          ATA_DIOW=0;
          delay_us(1);
          ATA_DIOW=1;
          }

void set_cdrom_reg_addr(Uchar Data){
          ATA_ADDR|=Data;
          }
///////////////////////////////////////
/*        cylinder register          */
///////////////////////////////////////
Uchar get_cyl_low_register(void){
          Uchar Temp;
          set_cdrom_reg_addr(CYLINDER_LOW_REG);
          Temp=read_cycle_l();
          return(Temp);
          }

Uchar get_cyl_high_register(void){
          Uchar Temp;
          set_cdrom_reg_addr(CYLINDER_HIGH_REG);
          Temp=read_cycle_l();
          return(Temp);
          }

void set_cyl_low_register(Uchar Data){
          set_cdrom_reg_addr(CYLINDER_LOW_REG);
          write_cycle_l(Data);
          }

void set_cyl_high_register(Uchar Data){
          set_cdrom_reg_addr(CYLINDER_HIGH_REG);
          write_cycle_l(Data);
          }
///////////////////////////////////////
/*         command register          */
///////////////////////////////////////
void set_command_register(Uchar Data){
          set_cdrom_reg_addr(COMMADN_REG);
          write_cycle_l(Data);
          }

Uchar get_status_register(void){
          Uchar Temp;
          set_cdrom_reg_addr(COMMADN_REG);
          Temp=read_cycle_l();
          return(Temp);
          }

void busy_wait(void){
          Uchar Temp;
          Temp=get_status_register();
          while(Temp&&STATUS_REG_BSY){
              delay_us(5);
              Temp=get_status_register();
              }
          }

void bsy_drdy_wait(void){
          Uchar Temp;
          busy_wait();
          while(Temp&&STATUS_REG_DRDY){
              delay_us(5);
              Temp=get_status_register();
              }
          }

void drq_wait(void){
          Uchar Temp;
          busy_wait();
          while(Temp&&STATUS_REG_DRQ){
              delay_us(5);
              Temp=get_status_register();
              }
          }

///////////////////////////////////////
/*       device/head  register       */
///////////////////////////////////////
Uchar get_devhead_register(void){
          Uchar Temp;
  	      set_cdrom_reg_addr(COMMADN_REG);
          Temp=read_cycle_l();
          return(Temp);
          }

void set_devhead_register(Uchar Data){
  	      set_cdrom_reg_addr(COMMADN_REG);
          write_cycle_l(Data);
          }
///////////////////////////////////////
/*            data register          */
///////////////////////////////////////

Uint get_data(void){
          Uint Temp;
          set_cdrom_reg_addr(DATA_REG);
          Temp=read_cycle();
          return(Temp);
          }

void set_data(Uint Data){
          set_cdrom_reg_addr(DATA_REG);
   	      write_cycle(Data);
   	      }

void set_data_ls(Uchar Data){
          set_cdrom_reg_addr(DATA_REG);
          write_cycle_l(Data);
          }

///////////////////////////////////////
/*           error register          */
///////////////////////////////////////

void set_error_register(Uchar Data){
          set_cdrom_reg_addr(ERROR_REG);
          write_cycle_l(Data);
          }

void main(void){
          delay_ms(30);
          while(1);
          }