usb245.map.rpt

基于ALTERA CYCLONE 系列的一个USB实验例程

+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 18    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 8     ;
; Number of registers using Output Enable      ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-----------+
; Hierarchy ;
+-----------+
usb245i


+-----------------------------------------------------------------------------------------------------------------+
; State Machine - curr_state                                                                                      ;
+-----------------+---------------+---------------+---------------+---------------+---------------+---------------+
; Name            ; curr_state~34 ; curr_state~33 ; curr_state~32 ; curr_state~31 ; curr_state~30 ; curr_state~29 ;
+-----------------+---------------+---------------+---------------+---------------+---------------+---------------+
; curr_state.st0  ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ;
; curr_state.st01 ; 0             ; 0             ; 0             ; 0             ; 1             ; 1             ;
; curr_state.st02 ; 0             ; 0             ; 0             ; 1             ; 0             ; 1             ;
; curr_state.st11 ; 0             ; 0             ; 1             ; 0             ; 0             ; 1             ;
; curr_state.st12 ; 0             ; 1             ; 0             ; 0             ; 0             ; 1             ;
; curr_state.st13 ; 1             ; 0             ; 0             ; 0             ; 0             ; 1             ;
+-----------------+---------------+---------------+---------------+---------------+---------------+---------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                       ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; |usb245i                   ; 28 (28)     ; 26           ; 0           ; 32   ; 0            ; 2 (2)        ; 10 (10)           ; 16 (16)          ; 0 (0)           ; |usb245i            ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/USB1C6/usb245.map.eqn.


+-----------------------------------------+
; Analysis & Synthesis Source Files Read  ;
+-----------------------+-----------------+
; File Name             ; Used in Netlist ;
+-----------------------+-----------------+
; D:/USB1C6/usb245i.vhd ; yes             ;
+-----------------------+-----------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------+-----------+
; Resource                        ; Usage     ;
+---------------------------------+-----------+
; Logic cells                     ; 28        ;
; Total combinational functions   ; 18        ;
; Total 4-input functions         ; 12        ;
; Total 3-input functions         ; 1         ;
; Total 2-input functions         ; 5         ;
; Total 1-input functions         ; 0         ;
; Total 0-input functions         ; 0         ;
; Combinational cells for routing ; 0         ;
; Total registers                 ; 26        ;
; I/O pins                        ; 32        ;
; Maximum fan-out node            ; clk       ;
; Maximum fan-out                 ; 26        ;
; Total fan-out                   ; 149       ;
; Average fan-out                 ; 2.48      ;
+---------------------------------+-----------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
    Info: Processing started: Wed Jun 01 12:32:45 2005
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off usb245 -c usb245
Info: Using design file usb245i.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: usb245i-usb245_arch
    Info: Found entity 1: usb245i
Info: VHDL Case Statement information at usb245i.vhd(106): OTHERS choice is never selected
Info: Duplicate registers merged to single register
    Info: Duplicate register process0~2 merged to single register process0~0
    Info: Duplicate register process0~4 merged to single register process0~0
    Info: Duplicate register process0~6 merged to single register process0~0
    Info: Duplicate register process0~8 merged to single register process0~0
    Info: Duplicate register process0~10 merged to single register process0~0
    Info: Duplicate register process0~12 merged to single register process0~0
    Info: Duplicate register process0~14 merged to single register process0~0
Info: State machine |usb245i|curr_state contains 6 states and 0 state bits
Info: Selected Auto state machine encoding method for state machine |usb245i|curr_state
Info: Encoding result for state machine |usb245i|curr_state
    Info: Completed encoding using 6 state bits
        Info: Encoded state bit curr_state~34
        Info: Encoded state bit curr_state~33
        Info: Encoded state bit curr_state~32
        Info: Encoded state bit curr_state~31
        Info: Encoded state bit curr_state~30
        Info: Encoded state bit curr_state~29
    Info: State |usb245i|curr_state.st0 uses code string 000000
    Info: State |usb245i|curr_state.st01 uses code string 000011
    Info: State |usb245i|curr_state.st02 uses code string 000101
    Info: State |usb245i|curr_state.st11 uses code string 001001
    Info: State |usb245i|curr_state.st12 uses code string 010001
    Info: State |usb245i|curr_state.st13 uses code string 100001
Info: Duplicate registers merged to single register
    Info: Duplicate register curr_state~34 merged to single register usb_wr~reg0
    Info: Duplicate register curr_state~31 merged to single register usb_rd~reg0, power-up level changed
Warning: Output pins are stuck at VCC or GND
    Warning: Pin usb_siwu stuck at VCC
Info: Registers with preset signals will power-up high
Info: Implemented 60 device resources after synthesis - the final resource count might be different
    Info: Implemented 13 input pins
    Info: Implemented 11 output pins
    Info: Implemented 8 bidirectional pins
    Info: Implemented 28 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings
    Info: Processing ended: Wed Jun 01 12:32:48 2005
    Info: Elapsed time: 00:00:02