usb245i.vhd

基于ALTERA CYCLONE 系列的一个USB实验例程

-- Mode: No.1

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE	ieee.std_logic_unsigned.all;


ENTITY usb245i IS
	PORT
	(
		 clk : IN STD_LOGIC;
		reset : in std_logic;
		
		usb_d : inout std_logic_vector(7 downto 0);
		usb_txe : in std_logic;
		usb_rxe : std_logic;
		usb_wr : out std_logic;
		usb_rd : out std_logic;
		usb_siwu : out std_logic;
		
		sendkey : in std_logic;
		senddata : IN std_logic_vector(7 downto 0);
		recvdata : OUT STD_LOGIC_VECTOR(7 downto 0)
	);
	
END usb245i;


ARCHITECTURE usb245_arch OF usb245i IS
	type ft245_state is (st0,st01,st02,st11,st12,st13);
	signal curr_state  : ft245_state;
	signal sendkeyr,sendkeyp,sendkeyd : std_logic;
	
BEGIN
usb_siwu <= '1';
process(clk,reset) begin
	if reset = '1' then
		curr_state <= st0;
		usb_wr <= '0';
		usb_rd <= '1';
		usb_d <= (others => 'Z');
		sendkeyr <= '1';
	elsif rising_edge(clk) then
		usb_wr <= '0';
		usb_rd <= '1';
		usb_d <= (others => 'Z');
		sendkeyr <= '0';
		case curr_state is
			when st0 => 
				if sendkeyp = '1' then
					curr_state <= st11;
					sendkeyr <= '1';
				elsif usb_rxe = '0' then
					curr_state <= st01;
				else
					curr_state <= st0;
				end if;
			when st01 => 
				usb_rd <= '0';
				curr_state <= st02;
			when st02 =>
				recvdata <= usb_d;
				curr_state <= st0;
			when st11 =>
				if usb_txe = '1' then
					curr_state <= st11;
				else
					usb_d <= senddata;
					curr_state <= st12;
				end if;
			when st12 =>
				usb_d <= senddata;
				usb_wr <= '1';
				curr_state <= st13;
			when st13 =>
				usb_d <= senddata;
				curr_state <= st0;
			when others => curr_state <= st0;
		end case;
	end if;
end process;

process(clk,reset) begin
	if reset = '1' then
		sendkeyd <= '1';
		sendkeyp <= '0';
	elsif rising_edge(clk) then
		sendkeyd <= sendkey;
		if sendkeyr = '1' then
			sendkeyd <= '1';
			sendkeyp <= '0';
		elsif sendkeyd = '0' and sendkey = '1' then
			sendkeyp <= '1';
		end if;
	end if;
end process;

			

END usb245_arch;