abc.ptf

基于ALTERA CYCLONE 系列的一个USB实验例程

SYSTEM abc
{
   WIZARD_SCRIPT_ARGUMENTS 
   {
      device_family = "ACEX1K";
      clock_freq = "50000000";
      generate_hdl = "1";
      generate_sdk = "1";
      do_build_sim = "1";
      hardcopy_compatible = "0";
      board_class = "";
      CLOCKS 
      {
         clk = "50000000";
      }
      hdl_language = "verilog";
      device_family_id = "ACEX1K";
      view_master_columns = "1";
      view_master_priorities = "0";
      name_column_width = "154";
      desc_column_width = "154";
      bustype_column_width = "0";
      base_column_width = "85";
      clock_column_width = "80";
      end_column_width = "85";
   }
}