usb245.tan.rpt

基于ALTERA CYCLONE 系列的一个USB实验例程

; N/A           ; None        ; -5.992 ns ; reset       ; recvdata[0]~reg0 ; clk      ;
; N/A           ; None        ; -6.271 ns ; usb_txe     ; process0~0       ; clk      ;
; N/A           ; None        ; -6.355 ns ; senddata[7] ; usb_d[7]~reg0    ; clk      ;
; N/A           ; None        ; -6.837 ns ; usb_txe     ; curr_state~32    ; clk      ;
; N/A           ; None        ; -6.839 ns ; usb_txe     ; curr_state~33    ; clk      ;
+---------------+-------------+-----------+-------------+------------------+----------+


+-------------------------------------------------------------------------------------------------+
; Minimum tco                                                                                     ;
+---------------+------------------+----------------+------------------+-------------+------------+
; Minimum Slack ; Required Min tco ; Actual Min tco ; From             ; To          ; From Clock ;
+---------------+------------------+----------------+------------------+-------------+------------+
; N/A           ; None             ; 7.041 ns       ; usb_d[3]~reg0    ; usb_d[3]    ; clk        ;
; N/A           ; None             ; 7.105 ns       ; usb_d[1]~reg0    ; usb_d[1]    ; clk        ;
; N/A           ; None             ; 7.249 ns       ; process0~0       ; usb_d[3]    ; clk        ;
; N/A           ; None             ; 7.262 ns       ; process0~0       ; usb_d[1]    ; clk        ;
; N/A           ; None             ; 7.318 ns       ; usb_d[6]~reg0    ; usb_d[6]    ; clk        ;
; N/A           ; None             ; 7.358 ns       ; usb_d[5]~reg0    ; usb_d[5]    ; clk        ;
; N/A           ; None             ; 7.476 ns       ; usb_d[4]~reg0    ; usb_d[4]    ; clk        ;
; N/A           ; None             ; 7.506 ns       ; process0~0       ; usb_d[5]    ; clk        ;
; N/A           ; None             ; 7.675 ns       ; process0~0       ; usb_d[6]    ; clk        ;
; N/A           ; None             ; 7.675 ns       ; process0~0       ; usb_d[4]    ; clk        ;
; N/A           ; None             ; 7.856 ns       ; usb_d[7]~reg0    ; usb_d[7]    ; clk        ;
; N/A           ; None             ; 7.858 ns       ; usb_rd~reg0      ; usb_rd      ; clk        ;
; N/A           ; None             ; 7.972 ns       ; process0~0       ; usb_d[7]    ; clk        ;
; N/A           ; None             ; 8.139 ns       ; usb_d[2]~reg0    ; usb_d[2]    ; clk        ;
; N/A           ; None             ; 8.147 ns       ; usb_d[0]~reg0    ; usb_d[0]    ; clk        ;
; N/A           ; None             ; 8.332 ns       ; process0~0       ; usb_d[2]    ; clk        ;
; N/A           ; None             ; 8.421 ns       ; usb_wr~reg0      ; usb_wr      ; clk        ;
; N/A           ; None             ; 8.475 ns       ; recvdata[0]~reg0 ; recvdata[0] ; clk        ;
; N/A           ; None             ; 8.651 ns       ; process0~0       ; usb_d[0]    ; clk        ;
; N/A           ; None             ; 8.892 ns       ; recvdata[1]~reg0 ; recvdata[1] ; clk        ;
; N/A           ; None             ; 8.905 ns       ; recvdata[3]~reg0 ; recvdata[3] ; clk        ;
; N/A           ; None             ; 8.909 ns       ; recvdata[4]~reg0 ; recvdata[4] ; clk        ;
; N/A           ; None             ; 8.926 ns       ; recvdata[5]~reg0 ; recvdata[5] ; clk        ;
; N/A           ; None             ; 8.931 ns       ; recvdata[7]~reg0 ; recvdata[7] ; clk        ;
; N/A           ; None             ; 8.941 ns       ; recvdata[6]~reg0 ; recvdata[6] ; clk        ;
; N/A           ; None             ; 8.946 ns       ; recvdata[2]~reg0 ; recvdata[2] ; clk        ;
+---------------+------------------+----------------+------------------+-------------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
    Info: Processing started: Wed Jun 01 12:33:01 2005
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off usb245 -c usb245 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node clk is an undefined clock
Info: Clock clk Internal fmax is restricted to 275.03 MHz between source register curr_state~29 and destination register curr_state~29
    Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.985 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X23_Y17_N8; Fanout = 4; REG Node = 'curr_state~29'
            Info: 2: + IC(0.873 ns) + CELL(0.114 ns) = 0.987 ns; Loc. = LC_X22_Y17_N7; Fanout = 1; COMB Node = 'Select~295'
            Info: 3: + IC(0.689 ns) + CELL(0.309 ns) = 1.985 ns; Loc. = LC_X23_Y17_N8; Fanout = 4; REG Node = 'curr_state~29'
            Info: Total cell delay = 0.423 ns ( 21.31 % )
            Info: Total interconnect delay = 1.562 ns ( 78.69 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock clk to destination register is 2.938 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 26; CLK Node = 'clk'
                Info: 2: + IC(0.758 ns) + CELL(0.711 ns) = 2.938 ns; Loc. = LC_X23_Y17_N8; Fanout = 4; REG Node = 'curr_state~29'
                Info: Total cell delay = 2.180 ns ( 74.20 % )
                Info: Total interconnect delay = 0.758 ns ( 25.80 % )
            Info: - Longest clock path from clock clk to source register is 2.938 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 26; CLK Node = 'clk'
                Info: 2: + IC(0.758 ns) + CELL(0.711 ns) = 2.938 ns; Loc. = LC_X23_Y17_N8; Fanout = 4; REG Node = 'curr_state~29'
                Info: Total cell delay = 2.180 ns ( 74.20 % )
                Info: Total interconnect delay = 0.758 ns ( 25.80 % )
        Info: + Micro clock to output delay of source is 0.224 ns
        Info: + Micro setup delay of destination is 0.037 ns
Info: tsu for register curr_state~33 (data pin = usb_txe, clock pin = clk) is 6.891 ns
    Info: + Longest pin to register delay is 9.792 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_23; Fanout = 3; PIN Node = 'usb_txe'
        Info: 2: + IC(7.585 ns) + CELL(0.738 ns) = 9.792 ns; Loc. = LC_X21_Y17_N5; Fanout = 10; REG Node = 'curr_state~33'
        Info: Total cell delay = 2.207 ns ( 22.54 % )
        Info: Total interconnect delay = 7.585 ns ( 77.46 % )
    Info: + Micro setup delay of destination is 0.037 ns
    Info: - Shortest clock path from clock clk to destination register is 2.938 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 26; CLK Node = 'clk'
        Info: 2: + IC(0.758 ns) + CELL(0.711 ns) = 2.938 ns; Loc. = LC_X21_Y17_N5; Fanout = 10; REG Node = 'curr_state~33'
        Info: Total cell delay = 2.180 ns ( 74.20 % )
        Info: Total interconnect delay = 0.758 ns ( 25.80 % )
Info: tco from clock clk to destination pin recvdata[2] through register recvdata[2]~reg0 is 8.946 ns
    Info: + Longest clock path from clock clk to source register is 2.938 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 26; CLK Node = 'clk'
        Info: 2: + IC(0.758 ns) + CELL(0.711 ns) = 2.938 ns; Loc. = LC_X23_Y17_N9; Fanout = 1; REG Node = 'recvdata[2]~reg0'
        Info: Total cell delay = 2.180 ns ( 74.20 % )
        Info: Total interconnect delay = 0.758 ns ( 25.80 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 5.784 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X23_Y17_N9; Fanout = 1; REG Node = 'recvdata[2]~reg0'
        Info: 2: + IC(3.660 ns) + CELL(2.124 ns) = 5.784 ns; Loc. = PIN_15; Fanout = 0; PIN Node = 'recvdata[2]'
        Info: Total cell delay = 2.124 ns ( 36.72 % )
        Info: Total interconnect delay = 3.660 ns ( 63.28 % )
Info: th for register recvdata[3]~reg0 (data pin = usb_d[3], clock pin = clk) is -4.035 ns
    Info: + Longest clock path from clock clk to destination register is 2.938 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 26; CLK Node = 'clk'
        Info: 2: + IC(0.758 ns) + CELL(0.711 ns) = 2.938 ns; Loc. = LC_X23_Y17_N1; Fanout = 1; REG Node = 'recvdata[3]~reg0'
        Info: Total cell delay = 2.180 ns ( 74.20 % )
        Info: Total interconnect delay = 0.758 ns ( 25.80 % )
    Info: + Micro hold delay of destination is 0.015 ns
    Info: - Shortest pin to register delay is 6.988 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_207; Fanout = 1; PIN Node = 'usb_d[3]'
        Info: 2: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = IOC_X20_Y21_N1; Fanout = 1; COMB Node = 'usb_d[3]~4'
        Info: 3: + IC(5.398 ns) + CELL(0.115 ns) = 6.988 ns; Loc. = LC_X23_Y17_N1; Fanout = 1; REG Node = 'recvdata[3]~reg0'
        Info: Total cell delay = 1.590 ns ( 22.75 % )
        Info: Total interconnect delay = 5.398 ns ( 77.25 % )
Info: Minimum tco from clock clk to destination pin usb_d[3] through register usb_d[3]~reg0 is 7.041 ns
    Info: + Shortest clock path from clock clk to source register is 2.938 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 26; CLK Node = 'clk'
        Info: 2: + IC(0.758 ns) + CELL(0.711 ns) = 2.938 ns; Loc. = LC_X22_Y17_N2; Fanout = 1; REG Node = 'usb_d[3]~reg0'
        Info: Total cell delay = 2.180 ns ( 74.20 % )
        Info: Total interconnect delay = 0.758 ns ( 25.80 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Shortest register to pin delay is 3.879 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X22_Y17_N2; Fanout = 1; REG Node = 'usb_d[3]~reg0'
        Info: 2: + IC(1.771 ns) + CELL(2.108 ns) = 3.879 ns; Loc. = PIN_207; Fanout = 0; PIN Node = 'usb_d[3]'
        Info: Total cell delay = 2.108 ns ( 54.34 % )
        Info: Total interconnect delay = 1.771 ns ( 45.66 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Wed Jun 01 12:33:01 2005
    Info: Elapsed time: 00:00:00