📄 bm.vhd
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library ieee; --38KHz
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity bm is
port(clk,d,en:in std_logic;
bianma,en_ad,clk_out:out std_logic;
data:out std_logic_vector(15 downto 0));
end;
architecture one of bm is
signal cnt1:std_logic_vector(6 downto 0);
signal cnt2:std_logic_vector(6 downto 0);
signal cnt3:std_logic_vector(8 downto 0);
signal cnt4:std_logic_vector(8 downto 0);
constant f1:integer:=21
begin
process(en)
if en'event and en='1' then
if cnt3=
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