hw2.fit.qmsg

用NEC编码方式写的红外发送程序,包括三个部分,分频,编码,编码输出

{ "Extra Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" 1 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0 0 "Finished moving registers into I/O cells, LUTs, and RAM blocks" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" {  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "5.737 ns register register " "Info: Estimated most critical path is register to register delay of 5.737 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns bm2:inst\|cnt2\[4\] 1 REG LAB_X38_Y17 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X38_Y17; Fanout = 5; REG Node = 'bm2:inst\|cnt2\[4\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { bm2:inst|cnt2[4] } "NODE_NAME" } } { "bm2.vhd" "" { Text "E:/altera/work/hw2/bm2.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.855 ns) + CELL(0.114 ns) 0.969 ns bm2:inst\|Equal4~88 2 COMB LAB_X39_Y17 1 " "Info: 2: + IC(0.855 ns) + CELL(0.114 ns) = 0.969 ns; Loc. = LAB_X39_Y17; Fanout = 1; COMB Node = 'bm2:inst\|Equal4~88'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.969 ns" { bm2:inst|cnt2[4] bm2:inst|Equal4~88 } "NODE_NAME" } } { "e:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1837 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.211 ns) + CELL(0.442 ns) 1.622 ns bm2:inst\|Equal4~89 3 COMB LAB_X39_Y17 12 " "Info: 3: + IC(0.211 ns) + CELL(0.442 ns) = 1.622 ns; Loc. = LAB_X39_Y17; Fanout = 12; COMB Node = 'bm2:inst\|Equal4~89'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.653 ns" { bm2:inst|Equal4~88 bm2:inst|Equal4~89 } "NODE_NAME" } } { "e:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1837 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.158 ns) + CELL(0.114 ns) 2.894 ns bm2:inst\|Selector31~451 4 COMB LAB_X43_Y17 13 " "Info: 4: + IC(1.158 ns) + CELL(0.114 ns) = 2.894 ns; Loc. = LAB_X43_Y17; Fanout = 13; COMB Node = 'bm2:inst\|Selector31~451'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.272 ns" { bm2:inst|Equal4~89 bm2:inst|Selector31~451 } "NODE_NAME" } } { "bm2.vhd" "" { Text "E:/altera/work/hw2/bm2.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.900 ns) + CELL(0.442 ns) 4.236 ns bm2:inst\|Selector9~428 5 COMB LAB_X43_Y16 1 " "Info: 5: + IC(0.900 ns) + CELL(0.442 ns) = 4.236 ns; Loc. = LAB_X43_Y16; Fanout = 1; COMB Node = 'bm2:inst\|Selector9~428'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.342 ns" { bm2:inst|Selector31~451 bm2:inst|Selector9~428 } "NODE_NAME" } } { "bm2.vhd" "" { Text "E:/altera/work/hw2/bm2.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.539 ns) + CELL(0.114 ns) 4.889 ns bm2:inst\|Selector9~429 6 COMB LAB_X43_Y16 1 " "Info: 6: + IC(0.539 ns) + CELL(0.114 ns) = 4.889 ns; Loc. = LAB_X43_Y16; Fanout = 1; COMB Node = 'bm2:inst\|Selector9~429'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.653 ns" { bm2:inst|Selector9~428 bm2:inst|Selector9~429 } "NODE_NAME" } } { "bm2.vhd" "" { Text "E:/altera/work/hw2/bm2.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.539 ns) + CELL(0.309 ns) 5.737 ns bm2:inst\|next_state.st9 7 REG LAB_X43_Y16 2 " "Info: 7: + IC(0.539 ns) + CELL(0.309 ns) = 5.737 ns; Loc. = LAB_X43_Y16; Fanout = 2; REG Node = 'bm2:inst\|next_state.st9'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.848 ns" { bm2:inst|Selector9~429 bm2:inst|next_state.st9 } "NODE_NAME" } } { "bm2.vhd" "" { Text "E:/altera/work/hw2/bm2.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.535 ns ( 26.76 % ) " "Info: Total cell delay = 1.535 ns ( 26.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.202 ns ( 73.24 % ) " "Info: Total interconnect delay = 4.202 ns ( 73.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.737 ns" { bm2:inst|cnt2[4] bm2:inst|Equal4~88 bm2:inst|Equal4~89 bm2:inst|Selector31~451 bm2:inst|Selector9~428 bm2:inst|Selector9~429 bm2:inst|next_state.st9 } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 2 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 2%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "x32_y14 x42_y27 " "Info: The peak interconnect region extends from location x32_y14 to location x42_y27" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Info: Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 26 12:58:03 2009 " "Info: Processing ended: Thu Mar 26 12:58:03 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Info: Elapsed time: 00:00:11" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/altera/work/hw2/hw2.fit.smsg " "Info: Generated suppressed messages file E:/altera/work/hw2/hw2.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}