hw2.tan.qmsg

用NEC编码方式写的红外发送程序,包括三个部分,分频,编码,编码输出

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk15 " "Info: Assuming node \"clk15\" is an undefined clock" {  } { { "hw2.bdf" "" { Schematic "E:/altera/work/hw2/hw2.bdf" { { 160 -8 160 176 "clk15" "" } } } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk15" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "pin233_en " "Info: Assuming node \"pin233_en\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "hw2.bdf" "" { Schematic "E:/altera/work/hw2/hw2.bdf" { { 184 -8 160 200 "pin233_en" "" } } } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "fenpin:inst1\|clk_temp " "Info: Detected ripple clock \"fenpin:inst1\|clk_temp\" as buffer" {  } { { "fenpin.vhd" "" { Text "E:/altera/work/hw2/fenpin.vhd" 15 -1 0 } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "fenpin:inst1\|clk_temp" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk15 register bm2:inst\|cnt2\[3\] register bm2:inst\|next_state.st33 149.84 MHz 6.674 ns Internal " "Info: Clock \"clk15\" has Internal fmax of 149.84 MHz between source register \"bm2:inst\|cnt2\[3\]\" and destination register \"bm2:inst\|next_state.st33\" (period= 6.674 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.413 ns + Longest register register " "Info: + Longest register to register delay is 6.413 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns bm2:inst\|cnt2\[3\] 1 REG LC_X38_Y17_N4 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X38_Y17_N4; Fanout = 3; REG Node = 'bm2:inst\|cnt2\[3\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { bm2:inst|cnt2[3] } "NODE_NAME" } } { "bm2.vhd" "" { Text "E:/altera/work/hw2/bm2.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.196 ns) + CELL(0.292 ns) 1.488 ns bm2:inst\|Equal3~104 2 COMB LC_X39_Y17_N2 2 " "Info: 2: + IC(1.196 ns) + CELL(0.292 ns) = 1.488 ns; Loc. = LC_X39_Y17_N2; Fanout = 2; COMB Node = 'bm2:inst\|Equal3~104'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.488 ns" { bm2:inst|cnt2[3] bm2:inst|Equal3~104 } "NODE_NAME" } } { "e:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1837 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.458 ns) + CELL(0.292 ns) 2.238 ns bm2:inst\|Equal4~89 3 COMB LC_X39_Y17_N1 12 " "Info: 3: + IC(0.458 ns) + CELL(0.292 ns) = 2.238 ns; Loc. = LC_X39_Y17_N1; Fanout = 12; COMB Node = 'bm2:inst\|Equal4~89'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.750 ns" { bm2:inst|Equal3~104 bm2:inst|Equal4~89 } "NODE_NAME" } } { "e:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1837 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.194 ns) + CELL(0.292 ns) 3.724 ns bm2:inst\|Selector31~451 4 COMB LC_X43_Y17_N9 13 " "Info: 4: + IC(1.194 ns) + CELL(0.292 ns) = 3.724 ns; Loc. = LC_X43_Y17_N9; Fanout = 13; COMB Node = 'bm2:inst\|Selector31~451'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.486 ns" { bm2:inst|Equal4~89 bm2:inst|Selector31~451 } "NODE_NAME" } } { "bm2.vhd" "" { Text "E:/altera/work/hw2/bm2.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.454 ns) + CELL(0.590 ns) 4.768 ns bm2:inst\|Selector15~443 5 COMB LC_X43_Y17_N5 6 " "Info: 5: + IC(0.454 ns) + CELL(0.590 ns) = 4.768 ns; Loc. = LC_X43_Y17_N5; Fanout = 6; COMB Node = 'bm2:inst\|Selector15~443'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.044 ns" { bm2:inst|Selector31~451 bm2:inst|Selector15~443 } "NODE_NAME" } } { "bm2.vhd" "" { Text "E:/altera/work/hw2/bm2.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.167 ns) + CELL(0.478 ns) 6.413 ns bm2:inst\|next_state.st33 6 REG LC_X40_Y17_N2 2 " "Info: 6: + IC(1.167 ns) + CELL(0.478 ns) = 6.413 ns; Loc. = LC_X40_Y17_N2; Fanout = 2; REG Node = 'bm2:inst\|next_state.st33'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.645 ns" { bm2:inst|Selector15~443 bm2:inst|next_state.st33 } "NODE_NAME" } } { "bm2.vhd" "" { Text "E:/altera/work/hw2/bm2.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.944 ns ( 30.31 % ) " "Info: Total cell delay = 1.944 ns ( 30.31 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.469 ns ( 69.69 % ) " "Info: Total interconnect delay = 4.469 ns ( 69.69 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.413 ns" { bm2:inst|cnt2[3] bm2:inst|Equal3~104 bm2:inst|Equal4~89 bm2:inst|Selector31~451 bm2:inst|Selector15~443 bm2:inst|next_state.st33 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "6.413 ns" { bm2:inst|cnt2[3] bm2:inst|Equal3~104 bm2:inst|Equal4~89 bm2:inst|Selector31~451 bm2:inst|Selector15~443 bm2:inst|next_state.st33 } { 0.000ns 1.196ns 0.458ns 1.194ns 0.454ns 1.167ns } { 0.000ns 0.292ns 0.292ns 0.292ns 0.590ns 0.478ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk15 destination 7.745 ns + Shortest register " "Info: + Shortest clock path from clock \"clk15\" to destination register is 7.745 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk15 1 CLK PIN_28 6 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 6; CLK Node = 'clk15'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk15 } "NODE_NAME" } } { "hw2.bdf" "" { Schematic "E:/altera/work/hw2/hw2.bdf" { { 160 -8 160 176 "clk15" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.031 ns) + CELL(0.935 ns) 3.435 ns fenpin:inst1\|clk_temp 2 REG LC_X8_Y13_N4 70 " "Info: 2: + IC(1.031 ns) + CELL(0.935 ns) = 3.435 ns; Loc. = LC_X8_Y13_N4; Fanout = 70; REG Node = 'fenpin:inst1\|clk_temp'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.966 ns" { clk15 fenpin:inst1|clk_temp } "NODE_NAME" } } { "fenpin.vhd" "" { Text "E:/altera/work/hw2/fenpin.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.599 ns) + CELL(0.711 ns) 7.745 ns bm2:inst\|next_state.st33 3 REG LC_X40_Y17_N2 2 " "Info: 3: + IC(3.599 ns) + CELL(0.711 ns) = 7.745 ns; Loc. = LC_X40_Y17_N2; Fanout = 2; REG Node = 'bm2:inst\|next_state.st33'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.310 ns" { fenpin:inst1|clk_temp bm2:inst|next_state.st33 } "NODE_NAME" } } { "bm2.vhd" "" { Text "E:/altera/work/hw2/bm2.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 40.22 % ) " "Info: Total cell delay = 3.115 ns ( 40.22 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.630 ns ( 59.78 % ) " "Info: Total interconnect delay = 4.630 ns ( 59.78 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.745 ns" { clk15 fenpin:inst1|clk_temp bm2:inst|next_state.st33 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "7.745 ns" { clk15 clk15~out0 fenpin:inst1|clk_temp bm2:inst|next_state.st33 } { 0.000ns 0.000ns 1.031ns 3.599ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk15 source 7.745 ns - Longest register " "Info: - Longest clock path from clock \"clk15\" to source register is 7.745 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk15 1 CLK PIN_28 6 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 6; CLK Node = 'clk15'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk15 } "NODE_NAME" } } { "hw2.bdf" "" { Schematic "E:/altera/work/hw2/hw2.bdf" { { 160 -8 160 176 "clk15" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.031 ns) + CELL(0.935 ns) 3.435 ns fenpin:inst1\|clk_temp 2 REG LC_X8_Y13_N4 70 " "Info: 2: + IC(1.031 ns) + CELL(0.935 ns) = 3.435 ns; Loc. = LC_X8_Y13_N4; Fanout = 70; REG Node = 'fenpin:inst1\|clk_temp'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.966 ns" { clk15 fenpin:inst1|clk_temp } "NODE_NAME" } } { "fenpin.vhd" "" { Text "E:/altera/work/hw2/fenpin.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.599 ns) + CELL(0.711 ns) 7.745 ns bm2:inst\|cnt2\[3\] 3 REG LC_X38_Y17_N4 3 " "Info: 3: + IC(3.599 ns) + CELL(0.711 ns) = 7.745 ns; Loc. = LC_X38_Y17_N4; Fanout = 3; REG Node = 'bm2:inst\|cnt2\[3\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.310 ns" { fenpin:inst1|clk_temp bm2:inst|cnt2[3] } "NODE_NAME" } } { "bm2.vhd" "" { Text "E:/altera/work/hw2/bm2.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 40.22 % ) " "Info: Total cell delay = 3.115 ns ( 40.22 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.630 ns ( 59.78 % ) " "Info: Total interconnect delay = 4.630 ns ( 59.78 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.745 ns" { clk15 fenpin:inst1|clk_temp bm2:inst|cnt2[3] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "7.745 ns" { clk15 clk15~out0 fenpin:inst1|clk_temp bm2:inst|cnt2[3] } { 0.000ns 0.000ns 1.031ns 3.599ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.745 ns" { clk15 fenpin:inst1|clk_temp bm2:inst|next_state.st33 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "7.745 ns" { clk15 clk15~out0 fenpin:inst1|clk_temp bm2:inst|next_state.st33 } { 0.000ns 0.000ns 1.031ns 3.599ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.745 ns" { clk15 fenpin:inst1|clk_temp bm2:inst|cnt2[3] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "7.745 ns" { clk15 clk15~out0 fenpin:inst1|clk_temp bm2:inst|cnt2[3] } { 0.000ns 0.000ns 1.031ns 3.599ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "bm2.vhd" "" { Text "E:/altera/work/hw2/bm2.vhd" 27 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "bm2.vhd" "" { Text "E:/altera/work/hw2/bm2.vhd" 27 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.413 ns" { bm2:inst|cnt2[3] bm2:inst|Equal3~104 bm2:inst|Equal4~89 bm2:inst|Selector31~451 bm2:inst|Selector15~443 bm2:inst|next_state.st33 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "6.413 ns" { bm2:inst|cnt2[3] bm2:inst|Equal3~104 bm2:inst|Equal4~89 bm2:inst|Selector31~451 bm2:inst|Selector15~443 bm2:inst|next_state.st33 } { 0.000ns 1.196ns 0.458ns 1.194ns 0.454ns 1.167ns } { 0.000ns 0.292ns 0.292ns 0.292ns 0.590ns 0.478ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.745 ns" { clk15 fenpin:inst1|clk_temp bm2:inst|next_state.st33 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "7.745 ns" { clk15 clk15~out0 fenpin:inst1|clk_temp bm2:inst|next_state.st33 } { 0.000ns 0.000ns 1.031ns 3.599ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.745 ns" { clk15 fenpin:inst1|clk_temp bm2:inst|cnt2[3] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "7.745 ns" { clk15 clk15~out0 fenpin:inst1|clk_temp bm2:inst|cnt2[3] } { 0.000ns 0.000ns 1.031ns 3.599ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk15 pin36_zb bm2:inst\|clk_out 14.696 ns register " "Info: tco from clock \"clk15\" to destination pin \"pin36_zb\" through register \"bm2:inst\|clk_out\" is 14.696 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk15 source 7.745 ns + Longest register " "Info: + Longest clock path from clock \"clk15\" to source register is 7.745 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk15 1 CLK PIN_28 6 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 6; CLK Node = 'clk15'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk15 } "NODE_NAME" } } { "hw2.bdf" "" { Schematic "E:/altera/work/hw2/hw2.bdf" { { 160 -8 160 176 "clk15" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.031 ns) + CELL(0.935 ns) 3.435 ns fenpin:inst1\|clk_temp 2 REG LC_X8_Y13_N4 70 " "Info: 2: + IC(1.031 ns) + CELL(0.935 ns) = 3.435 ns; Loc. = LC_X8_Y13_N4; Fanout = 70; REG Node = 'fenpin:inst1\|clk_temp'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.966 ns" { clk15 fenpin:inst1|clk_temp } "NODE_NAME" } } { "fenpin.vhd" "" { Text "E:/altera/work/hw2/fenpin.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.599 ns) + CELL(0.711 ns) 7.745 ns bm2:inst\|clk_out 3 REG LC_X40_Y17_N5 7 " "Info: 3: + IC(3.599 ns) + CELL(0.711 ns) = 7.745 ns; Loc. = LC_X40_Y17_N5; Fanout = 7; REG Node = 'bm2:inst\|clk_out'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.310 ns" { fenpin:inst1|clk_temp bm2:inst|clk_out } "NODE_NAME" } } { "bm2.vhd" "" { Text "E:/altera/work/hw2/bm2.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 40.22 % ) " "Info: Total cell delay = 3.115 ns ( 40.22 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.630 ns ( 59.78 % ) " "Info: Total interconnect delay = 4.630 ns ( 59.78 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.745 ns" { clk15 fenpin:inst1|clk_temp bm2:inst|clk_out } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "7.745 ns" { clk15 clk15~out0 fenpin:inst1|clk_temp bm2:inst|clk_out } { 0.000ns 0.000ns 1.031ns 3.599ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "bm2.vhd" "" { Text "E:/altera/work/hw2/bm2.vhd" 6 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.727 ns + Longest register pin " "Info: + Longest register to pin delay is 6.727 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns bm2:inst\|clk_out 1 REG LC_X40_Y17_N5 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X40_Y17_N5; Fanout = 7; REG Node = 'bm2:inst\|clk_out'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { bm2:inst|clk_out } "NODE_NAME" } } { "bm2.vhd" "" { Text "E:/altera/work/hw2/bm2.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.286 ns) + CELL(0.114 ns) 1.400 ns zb:inst2\|zb1~0 2 COMB LC_X40_Y13_N2 1 " "Info: 2: + IC(1.286 ns) + CELL(0.114 ns) = 1.400 ns; Loc. = LC_X40_Y13_N2; Fanout = 1; COMB Node = 'zb:inst2\|zb1~0'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.400 ns" { bm2:inst|clk_out zb:inst2|zb1~0 } "NODE_NAME" } } { "zb.vhd" "" { Text "E:/altera/work/hw2/zb.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.203 ns) + CELL(2.124 ns) 6.727 ns pin36_zb 3 PIN PIN_141 0 " "Info: 3: + IC(3.203 ns) + CELL(2.124 ns) = 6.727 ns; Loc. = PIN_141; Fanout = 0; PIN Node = 'pin36_zb'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.327 ns" { zb:inst2|zb1~0 pin36_zb } "NODE_NAME" } } { "hw2.bdf" "" { Schematic "E:/altera/work/hw2/hw2.bdf" { { 160 656 832 176 "pin36_zb" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.238 ns ( 33.27 % ) " "Info: Total cell delay = 2.238 ns ( 33.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.489 ns ( 66.73 % ) " "Info: Total interconnect delay = 4.489 ns ( 66.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.727 ns" { bm2:inst|clk_out zb:inst2|zb1~0 pin36_zb } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "6.727 ns" { bm2:inst|clk_out zb:inst2|zb1~0 pin36_zb } { 0.000ns 1.286ns 3.203ns } { 0.000ns 0.114ns 2.124ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.745 ns" { clk15 fenpin:inst1|clk_temp bm2:inst|clk_out } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "7.745 ns" { clk15 clk15~out0 fenpin:inst1|clk_temp bm2:inst|clk_out } { 0.000ns 0.000ns 1.031ns 3.599ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.727 ns" { bm2:inst|clk_out zb:inst2|zb1~0 pin36_zb } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "6.727 ns" { bm2:inst|clk_out zb:inst2|zb1~0 pin36_zb } { 0.000ns 1.286ns 3.203ns } { 0.000ns 0.114ns 2.124ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}