hw2.map.qmsg

用NEC编码方式写的红外发送程序,包括三个部分,分频,编码,编码输出

{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "current_state.st27 bm2.vhd(338) " "Info (10041): Verilog HDL or VHDL info at bm2.vhd(338): inferred latch for \"current_state.st27\"" {  } { { "bm2.vhd" "" { Text "E:/altera/work/hw2/bm2.vhd" 338 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "current_state.st26 bm2.vhd(338) " "Info (10041): Verilog HDL or VHDL info at bm2.vhd(338): inferred latch for \"current_state.st26\"" {  } { { "bm2.vhd" "" { Text "E:/altera/work/hw2/bm2.vhd" 338 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "current_state.st25 bm2.vhd(338) " "Info (10041): Verilog HDL or VHDL info at bm2.vhd(338): inferred latch for \"current_state.st25\"" {  } { { "bm2.vhd" "" { Text "E:/altera/work/hw2/bm2.vhd" 338 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "current_state.st24 bm2.vhd(338) " "Info (10041): Verilog HDL or VHDL info at bm2.vhd(338): inferred latch for \"current_state.st24\"" {  } { { "bm2.vhd" "" { Text "E:/altera/work/hw2/bm2.vhd" 338 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "current_state.st23 bm2.vhd(338) " "Info (10041): Verilog HDL or VHDL info at bm2.vhd(338): inferred latch for \"current_state.st23\"" {  } { { "bm2.vhd" "" { Text "E:/altera/work/hw2/bm2.vhd" 338 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "current_state.st22 bm2.vhd(338) " "Info (10041): Verilog HDL or VHDL info at bm2.vhd(338): inferred latch for \"current_state.st22\"" {  } { { "bm2.vhd" "" { Text "E:/altera/work/hw2/bm2.vhd" 338 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "current_state.st21 bm2.vhd(338) " "Info (10041): Verilog HDL or VHDL info at bm2.vhd(338): inferred latch for \"current_state.st21\"" {  } { { "bm2.vhd" "" { Text "E:/altera/work/hw2/bm2.vhd" 338 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "current_state.st20 bm2.vhd(338) " "Info (10041): Verilog HDL or VHDL info at bm2.vhd(338): inferred latch for \"current_state.st20\"" {  } { { "bm2.vhd" "" { Text "E:/altera/work/hw2/bm2.vhd" 338 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "current_state.st19 bm2.vhd(338) " "Info (10041): Verilog HDL or VHDL info at bm2.vhd(338): inferred latch for \"current_state.st19\"" {  } { { "bm2.vhd" "" { Text "E:/altera/work/hw2/bm2.vhd" 338 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "current_state.st18 bm2.vhd(338) " "Info (10041): Verilog HDL or VHDL info at bm2.vhd(338): inferred latch for \"current_state.st18\"" {  } { { "bm2.vhd" "" { Text "E:/altera/work/hw2/bm2.vhd" 338 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "current_state.st17 bm2.vhd(338) " "Info (10041): Verilog HDL or VHDL info at bm2.vhd(338): inferred latch for \"current_state.st17\"" {  } { { "bm2.vhd" "" { Text "E:/altera/work/hw2/bm2.vhd" 338 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "current_state.st16 bm2.vhd(338) " "Info (10041): Verilog HDL or VHDL info at bm2.vhd(338): inferred latch for \"current_state.st16\"" {  } { { "bm2.vhd" "" { Text "E:/altera/work/hw2/bm2.vhd" 338 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "current_state.st15 bm2.vhd(338) " "Info (10041): Verilog HDL or VHDL info at bm2.vhd(338): inferred latch for \"current_state.st15\"" {  } { { "bm2.vhd" "" { Text "E:/altera/work/hw2/bm2.vhd" 338 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "current_state.st14 bm2.vhd(338) " "Info (10041): Verilog HDL or VHDL info at bm2.vhd(338): inferred latch for \"current_state.st14\"" {  } { { "bm2.vhd" "" { Text "E:/altera/work/hw2/bm2.vhd" 338 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "current_state.st13 bm2.vhd(338) " "Info (10041): Verilog HDL or VHDL info at bm2.vhd(338): inferred latch for \"current_state.st13\"" {  } { { "bm2.vhd" "" { Text "E:/altera/work/hw2/bm2.vhd" 338 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "current_state.st12 bm2.vhd(338) " "Info (10041): Verilog HDL or VHDL info at bm2.vhd(338): inferred latch for \"current_state.st12\"" {  } { { "bm2.vhd" "" { Text "E:/altera/work/hw2/bm2.vhd" 338 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "current_state.st11 bm2.vhd(338) " "Info (10041): Verilog HDL or VHDL info at bm2.vhd(338): inferred latch for \"current_state.st11\"" {  } { { "bm2.vhd" "" { Text "E:/altera/work/hw2/bm2.vhd" 338 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "current_state.st10 bm2.vhd(338) " "Info (10041): Verilog HDL or VHDL info at bm2.vhd(338): inferred latch for \"current_state.st10\"" {  } { { "bm2.vhd" "" { Text "E:/altera/work/hw2/bm2.vhd" 338 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "current_state.st9 bm2.vhd(338) " "Info (10041): Verilog HDL or VHDL info at bm2.vhd(338): inferred latch for \"current_state.st9\"" {  } { { "bm2.vhd" "" { Text "E:/altera/work/hw2/bm2.vhd" 338 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}