hw2.map.qmsg

用NEC编码方式写的红外发送程序,包括三个部分,分频,编码,编码输出

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version " "Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar 26 12:57:40 2009 " "Info: Processing started: Thu Mar 26 12:57:40 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off hw2 -c hw2 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off hw2 -c hw2" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "hw2.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file hw2.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 hw2 " "Info: Found entity 1: hw2" {  } { { "hw2.bdf" "" { Schematic "E:/altera/work/hw2/hw2.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "bm2.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file bm2.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 bm2-one " "Info: Found design unit 1: bm2-one" {  } { { "bm2.vhd" "" { Text "E:/altera/work/hw2/bm2.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 bm2 " "Info: Found entity 1: bm2" {  } { { "bm2.vhd" "" { Text "E:/altera/work/hw2/bm2.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fenpin.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file fenpin.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 fenpin-one " "Info: Found design unit 1: fenpin-one" {  } { { "fenpin.vhd" "" { Text "E:/altera/work/hw2/fenpin.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 fenpin " "Info: Found entity 1: fenpin" {  } { { "fenpin.vhd" "" { Text "E:/altera/work/hw2/fenpin.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "zb.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file zb.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 zb-one " "Info: Found design unit 1: zb-one" {  } { { "zb.vhd" "" { Text "E:/altera/work/hw2/zb.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 zb " "Info: Found entity 1: zb" {  } { { "zb.vhd" "" { Text "E:/altera/work/hw2/zb.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "hw2 " "Info: Elaborating entity \"hw2\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "zb zb:inst2 " "Info: Elaborating entity \"zb\" for hierarchy \"zb:inst2\"" {  } { { "hw2.bdf" "inst2" { Schematic "E:/altera/work/hw2/hw2.bdf" { { 136 520 616 232 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "zb1 zb.vhd(19) " "Warning (10631): VHDL Process Statement warning at zb.vhd(19): inferring latch(es) for signal or variable \"zb1\", which holds its previous value in one or more paths through the process" {  } { { "zb.vhd" "" { Text "E:/altera/work/hw2/zb.vhd" 19 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "zb1 zb.vhd(19) " "Info (10041): Verilog HDL or VHDL info at zb.vhd(19): inferred latch for \"zb1\"" {  } { { "zb.vhd" "" { Text "E:/altera/work/hw2/zb.vhd" 19 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bm2 bm2:inst " "Info: Elaborating entity \"bm2\" for hierarchy \"bm2:inst\"" {  } { { "hw2.bdf" "inst" { Schematic "E:/altera/work/hw2/hw2.bdf" { { 136 336 472 232 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "current_state bm2.vhd(338) " "Warning (10631): VHDL Process Statement warning at bm2.vhd(338): inferring latch(es) for signal or variable \"current_state\", which holds its previous value in one or more paths through the process" {  } { { "bm2.vhd" "" { Text "E:/altera/work/hw2/bm2.vhd" 338 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "current_state.st33 bm2.vhd(338) " "Info (10041): Verilog HDL or VHDL info at bm2.vhd(338): inferred latch for \"current_state.st33\"" {  } { { "bm2.vhd" "" { Text "E:/altera/work/hw2/bm2.vhd" 338 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "current_state.st32 bm2.vhd(338) " "Info (10041): Verilog HDL or VHDL info at bm2.vhd(338): inferred latch for \"current_state.st32\"" {  } { { "bm2.vhd" "" { Text "E:/altera/work/hw2/bm2.vhd" 338 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "current_state.st31 bm2.vhd(338) " "Info (10041): Verilog HDL or VHDL info at bm2.vhd(338): inferred latch for \"current_state.st31\"" {  } { { "bm2.vhd" "" { Text "E:/altera/work/hw2/bm2.vhd" 338 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "current_state.st30 bm2.vhd(338) " "Info (10041): Verilog HDL or VHDL info at bm2.vhd(338): inferred latch for \"current_state.st30\"" {  } { { "bm2.vhd" "" { Text "E:/altera/work/hw2/bm2.vhd" 338 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "current_state.st29 bm2.vhd(338) " "Info (10041): Verilog HDL or VHDL info at bm2.vhd(338): inferred latch for \"current_state.st29\"" {  } { { "bm2.vhd" "" { Text "E:/altera/work/hw2/bm2.vhd" 338 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "current_state.st28 bm2.vhd(338) " "Info (10041): Verilog HDL or VHDL info at bm2.vhd(338): inferred latch for \"current_state.st28\"" {  } { { "bm2.vhd" "" { Text "E:/altera/work/hw2/bm2.vhd" 338 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}