hw2.fnsim.qmsg

用NEC编码方式写的红外发送程序,包括三个部分,分频,编码,编码输出

{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "current_state.st17 bm2.vhd(338) " "Info (10041): Verilog HDL or VHDL info at bm2.vhd(338): inferred latch for \"current_state.st17\"" {  } { { "bm2.vhd" "" { Text "E:/altera/work/hw2/bm2.vhd" 338 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "current_state.st16 bm2.vhd(338) " "Info (10041): Verilog HDL or VHDL info at bm2.vhd(338): inferred latch for \"current_state.st16\"" {  } { { "bm2.vhd" "" { Text "E:/altera/work/hw2/bm2.vhd" 338 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "current_state.st15 bm2.vhd(338) " "Info (10041): Verilog HDL or VHDL info at bm2.vhd(338): inferred latch for \"current_state.st15\"" {  } { { "bm2.vhd" "" { Text "E:/altera/work/hw2/bm2.vhd" 338 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "current_state.st14 bm2.vhd(338) " "Info (10041): Verilog HDL or VHDL info at bm2.vhd(338): inferred latch for \"current_state.st14\"" {  } { { "bm2.vhd" "" { Text "E:/altera/work/hw2/bm2.vhd" 338 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "current_state.st13 bm2.vhd(338) " "Info (10041): Verilog HDL or VHDL info at bm2.vhd(338): inferred latch for \"current_state.st13\"" {  } { { "bm2.vhd" "" { Text "E:/altera/work/hw2/bm2.vhd" 338 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "current_state.st12 bm2.vhd(338) " "Info (10041): Verilog HDL or VHDL info at bm2.vhd(338): inferred latch for \"current_state.st12\"" {  } { { "bm2.vhd" "" { Text "E:/altera/work/hw2/bm2.vhd" 338 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "current_state.st11 bm2.vhd(338) " "Info (10041): Verilog HDL or VHDL info at bm2.vhd(338): inferred latch for \"current_state.st11\"" {  } { { "bm2.vhd" "" { Text "E:/altera/work/hw2/bm2.vhd" 338 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "current_state.st10 bm2.vhd(338) " "Info (10041): Verilog HDL or VHDL info at bm2.vhd(338): inferred latch for \"current_state.st10\"" {  } { { "bm2.vhd" "" { Text "E:/altera/work/hw2/bm2.vhd" 338 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "current_state.st9 bm2.vhd(338) " "Info (10041): Verilog HDL or VHDL info at bm2.vhd(338): inferred latch for \"current_state.st9\"" {  } { { "bm2.vhd" "" { Text "E:/altera/work/hw2/bm2.vhd" 338 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "current_state.st8 bm2.vhd(338) " "Info (10041): Verilog HDL or VHDL info at bm2.vhd(338): inferred latch for \"current_state.st8\"" {  } { { "bm2.vhd" "" { Text "E:/altera/work/hw2/bm2.vhd" 338 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "current_state.st7 bm2.vhd(338) " "Info (10041): Verilog HDL or VHDL info at bm2.vhd(338): inferred latch for \"current_state.st7\"" {  } { { "bm2.vhd" "" { Text "E:/altera/work/hw2/bm2.vhd" 338 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "current_state.st6 bm2.vhd(338) " "Info (10041): Verilog HDL or VHDL info at bm2.vhd(338): inferred latch for \"current_state.st6\"" {  } { { "bm2.vhd" "" { Text "E:/altera/work/hw2/bm2.vhd" 338 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "current_state.st5 bm2.vhd(338) " "Info (10041): Verilog HDL or VHDL info at bm2.vhd(338): inferred latch for \"current_state.st5\"" {  } { { "bm2.vhd" "" { Text "E:/altera/work/hw2/bm2.vhd" 338 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "current_state.st4 bm2.vhd(338) " "Info (10041): Verilog HDL or VHDL info at bm2.vhd(338): inferred latch for \"current_state.st4\"" {  } { { "bm2.vhd" "" { Text "E:/altera/work/hw2/bm2.vhd" 338 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "current_state.st3 bm2.vhd(338) " "Info (10041): Verilog HDL or VHDL info at bm2.vhd(338): inferred latch for \"current_state.st3\"" {  } { { "bm2.vhd" "" { Text "E:/altera/work/hw2/bm2.vhd" 338 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "current_state.st2 bm2.vhd(338) " "Info (10041): Verilog HDL or VHDL info at bm2.vhd(338): inferred latch for \"current_state.st2\"" {  } { { "bm2.vhd" "" { Text "E:/altera/work/hw2/bm2.vhd" 338 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "current_state.st1 bm2.vhd(338) " "Info (10041): Verilog HDL or VHDL info at bm2.vhd(338): inferred latch for \"current_state.st1\"" {  } { { "bm2.vhd" "" { Text "E:/altera/work/hw2/bm2.vhd" 338 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "current_state.st0 bm2.vhd(338) " "Info (10041): Verilog HDL or VHDL info at bm2.vhd(338): inferred latch for \"current_state.st0\"" {  } { { "bm2.vhd" "" { Text "E:/altera/work/hw2/bm2.vhd" 338 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fenpin fenpin:inst1 " "Info: Elaborating entity \"fenpin\" for hierarchy \"fenpin:inst1\"" {  } { { "hw2.bdf" "inst1" { Schematic "E:/altera/work/hw2/hw2.bdf" { { 136 208 304 232 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "zb:inst2\|c_c High " "Info: Power-up level of register \"zb:inst2\|c_c\" is not specified -- using power-up level of High to minimize register" {  } { { "zb.vhd" "" { Text "E:/altera/work/hw2/zb.vhd" 10 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "zb:inst2\|c_c data_in VCC " "Warning: Reduced register \"zb:inst2\|c_c\" with stuck data_in port to stuck value VCC" {  } { { "zb.vhd" "" { Text "E:/altera/work/hw2/zb.vhd" 10 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_USE_LATCH" "zb:inst2\|zb1 " "Warning: LATCH primitive \"zb:inst2\|zb1\" is permanently enabled" {  } { { "zb.vhd" "" { Text "E:/altera/work/hw2/zb.vhd" 6 -1 0 } }  } 0 0 "LATCH primitive \"%1!s!\" is permanently enabled" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../quartus60/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../quartus60/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "e:/altera/quartus60/libraries/megafunctions/lpm_add_sub.tdf" 100 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "fenpin:inst1\|lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"fenpin:inst1\|lpm_add_sub:Add0\"" {  } { { "e:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "e:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../quartus60/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../quartus60/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "e:/altera/quartus60/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "fenpin:inst1\|lpm_add_sub:Add0\|addcore:adder fenpin:inst1\|lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"fenpin:inst1\|lpm_add_sub:Add0\|addcore:adder\", which is child of megafunction instantiation \"fenpin:inst1\|lpm_add_sub:Add0\"" {  } { { "lpm_add_sub.tdf" "" { Text "e:/altera/quartus60/libraries/megafunctions/lpm_add_sub.tdf" 266 4 0 } } { "e:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "e:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "fenpin:inst1\|lpm_add_sub:Add0 " "Info: Instantiated megafunction \"fenpin:inst1\|lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 5 " "Info: Parameter \"LPM_WIDTH\" = \"5\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } { { "e:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "e:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../quartus60/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../quartus60/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "a_csnbuffer.tdf" "" { Text "e:/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "fenpin:inst1\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:oflow_node fenpin:inst1\|lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"fenpin:inst1\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"fenpin:inst1\|lpm_add_sub:Add0\"" {  } { { "addcore.tdf" "" { Text "e:/altera/quartus60/libraries/megafunctions/addcore.tdf" 94 2 0 } } { "e:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "e:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}