📄 p1_waveforms.html
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<title>Sample Waveforms for p1.vhd </title>
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<h2><CENTER>Sample behavioral waveforms for design file p1.vhd </CENTER></h2>
<P>The following waveforms show the behavior of altpll megafunction for the chosen set of parameters in design p1.vhd. The design p1.vhd has Cyclone AUTO pll configured in NORMAL mode The primary clock input to the PLL is INCLK0, with clock period 20000 ps. CLK0 multiply by = 1, CLK0 divide by = 1, CLK0 phase_shift = 0 Input port ARESET is used. This port is active high. When asserted, it will cause the LOCKED port and all CLK outputs to drop to zero. The PLL will relock to the input clock when this port is deasserted. Input port PLLENA is used. This port is active high. When deasserted, it will cause the PLL to unlock, and the LOCKED port and all CLK outputs will drop to zero. </P>
<CENTER><img src=p1_wave0.jpg> </CENTER>
<P><CENTER><FONT size=2>Fig. 1 : Wave showing NORMAL mode operation. </CENTER></P>
<P><FONT size=3></P>
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